Analysis of an efficient partial product reduction technique

Vyas, Keerti; Jain, Ginni; Maurya, Vijendra K; Mehra, Anu

doi:10.1109/icgciot.2015.7380417

Cited by 5 publications

(4 citation statements)

References 8 publications

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“…Vyas (2016) demonstrated the efficiency of compressed trees in their article [7] , while also presenting a method for reducing circuit area through the reuse of compressed circuits. Identifying the repeated functionality in the circuit and employing control signals for rotation-based utilization is the key to achieving reuse.…”

Section: Improved Partial Product Compression Strategymentioning

confidence: 99%

Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Su,

Xia,

Zhao

et al. 2023

International Conference on Electronic Materials and Information Engineering (EMIE 2023)

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Section: Improved Partial Product Compression Strategymentioning

confidence: 99%

Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Su,

Xia,

Zhao

et al. 2023

International Conference on Electronic Materials and Information Engineering (EMIE 2023)

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“…However, the gaps in speed and cost have not been analysed in that study. In [5], the authors have reported on an efficient methodology for partial product reduction in binary multipliers and claimed that the same was designed with 16 nm TSMH CMOS technology using the simulation tool Tanner EDA 14.1. The authors have also compared the various available methods of other multipliers.…”

Section: Literature Surveymentioning

confidence: 99%

“…For example, the multipliers developed in [2][3][4] perform partial product reduction using Wallace or Dadda multipliers, and thereafter, compressors are used to compress the results. Another design in [5] uses a combination of multiplier and compressor techniques to perform the partial product reduction segment. Most of the existing systems reviewed utilised Vedic mathematics for partial product generation.…”

Section: Background Of the Researchmentioning

confidence: 99%

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple-and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…Most of the multiplier systems reviewed in this paper carried out the processes of partial product generation, partial product storage and partial product reduction. For example, multipliers developed in [1], [40] and [41] perform partial product reduction using Wallace or Dadda multipliers, thereafter the results are compressed using compressors. Others like [3] [15]use a combination of multiplier and compressor techniques to perform the partial product reduction segment.…”

Section: Considerations For Development Of Novel Floating-point Multimentioning

confidence: 99%

Comparative Review of Floating-Point Multiplier Systems

George¹,

Tobago²

2019

IJHIT

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This paper presents a comprehensive comparative review of existing floating-point multiplier systems. The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some case are carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research are identified. This paper also serves to identify several recommendations and considerations for the development of a multi-precision floating point multiplier system capable of treating with the weaknesses of multiplier systems identified.

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Analysis of an efficient partial product reduction technique

Cited by 5 publications

References 8 publications

Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Comparative Review of Floating-Point Multiplier Systems

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