Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Abstract

We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

“…On-chip isolation technology is one of the most adequate approaches for realizing these requirements [15][16][17] and several on-chip isolation devices with a multi trench isolation structure have been reported. [18][19][20][21][22][23][24][25] Figure 2 shows a review status of multi trench gap isolation structures. [18][19][20][21][22][23][24][25] As for the basic structure (1), isolation resistance is very high, but breakdown voltage is very low, because the applied voltage over the multi trench isolation is not evenly shared by the parasitic capacitors existing in between siliconon-insulator (SOI) and a substrate.…”

“…[18][19][20][21][22][23][24][25] Figure 2 shows a review status of multi trench gap isolation structures. [18][19][20][21][22][23][24][25] As for the basic structure (1), isolation resistance is very high, but breakdown voltage is very low, because the applied voltage over the multi trench isolation is not evenly shared by the parasitic capacitors existing in between siliconon-insulator (SOI) and a substrate. 24) This limits breakdown voltage.…”