Analysis of copper grains in damascene trenches after rapid thermal processing or furnace anneals

Abstract

INTRODUCTIONCopper has ϳ40% lower electrical resistivity and about two orders of magnitude higher electromigration resistance than aluminum, 1,2 making it the metal of choice for high-performance interconnects at the 180-nm technology node and beyond. Understanding the relationship between interconnect metal microstructure and electrical properties can allow processing to be optimized to increase device yield and reliability. 3-6 This is particularly true for the electrochemically deposited Cu, the most practical and promising Cu deposition process for the current semiconductor industry.Electroplated Cu will undergo grain growth even at room temperature in blanket films and in damascene trenches due to the ample amount of interfa-cial energy stored in the as-plated, very fine initial grains, typically around 0.05 m or smaller. 7,8 Final grain size, crystal orientation, and Cu line tensile stress can be largely impacted by thermal cycles of subsequent processing. Earlier reports, by us and others, showed that the microstructure of Cu depended not only on anneal temperature, but also on temperature ramp rates and previous thermal processing. 6,9,10 The coefficient of thermal expansion (CTE) mismatch between Cu and the surrounding dielectric material makes the situation more complex. This CTE mismatch can cause large tensile stresses in the Cu lines and possible void formation, and via detachment, resulting in reliability issues, high line and via resistance, and low via chain yield. It is critical to understand the relationships between processing and microstructure, and the role of microstructure in determining device performance, yield, and reliability, in order to maximize the benefit of Cu metallization.The microstructures of Cu lines in damascene trenches annealed at temperatures from room temperature to 425°C using both rapid thermal processing (RTP) and furnace annealing were investigated using an array of characterization techniques including transmission electron microscopy (TEM), focused ion beam, scanning electron microscopy (SEM), and electron backscatter diffraction-orientation-imaging microscopy (EBSD-OIM). It was found that the final grain sizes strongly depend on the annealing process used; RTP generated larger grains than furnace annealing. The Cu line electrical resistance correlated with grain size differences observed for RTP and furnace anneals. The ramping rate, not the annealing time, played the critical role in the grain growth process. In either case, a high density of ⌺3 coincident site lattice (CSL) twin boundaries was observed in the Cu lines. Forty-five percent of the grain boundaries measured were found to be ⌺3 CSL twins, which are differentiated from random high-angle boundaries by having preferred electrical and diffusion properties. The minimum feature dimension of width or height of the damascene trenches limited the average grain size. Prior to the trench height limitation, the average grain size increased linearly with the trench width. The Cu (111) texture became stronger as th...

Crystal Structure Evolution of Individual Graphene Islands During CVD Growth on Copper Foil

“…After 30 min annealing at 1035 °C, the grain sizes are in a millimeter scale. Although the Cu (111) and (001) containing facets are enlarged, there is no particular preference for the growth of low‐index crystallographic (111) or (001) grains, consistent with previous results . To further evaluate the stability of certain Cu grains, we repeated the annealing process after the orientation measurement in Figure b.…”

“…In addition to the size, the 6‐lobed graphene islands exhibit a higher single‐crystal percentage than that of the 4‐lobed islands as shown in Table . We suppose that this is related to the suppressed surface pre‐melting for the close‐packed Cu (111) plane as well as the possibility of a significantly decreased binding energy (calculated as 33 meV per carbon atom) between graphene and Cu (111) containing facets compared with the binding energy between graphene and individual Cu atoms (1.814–1.981 eV) that are more likely to be present in the disordered regions of the Cu surface . Due to the suppressed surface pre‐melting and the lower binding energy, the Cu (111) plane is more stable and the graphene islands should be less affected by the Cu grain evolution.…”

Effects of thermally-induced changes of Cu grains on domain structure and electrical performance of CVD-grown graphene

“…1(b), consistent with previous reports. 26,27 To study the subsequent thermal effect on Cu grains, a 10 min annealing at 1000 °C was performed for the graphene-Cu sample (Experimental section) after the orientation measurement in Fig. 1(b).…”

Microstructure, Stress, and Stress-Induced Damages in Damascene Cu

“…This is because the initial grain size of electroplated Cu is as small as few tens nanometer [1] and grain growth occurs under the confinement by predefined trenches. The final grain size of Cu lines after annealing is known to be about its dimension of width [2], thus strain by volume shrinkage is considerably developed during grain growth. For example, Lee et al [3] reported that the growth stress in their electroplated Cu films was as large as 120MPa.…”