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Transformations in electroplated Cu films from a fine to course grain crystal structure (average grain sizes went from ∼0.1 µm to several microns) were observed to strongly depend on film thickness and geometry. Thinner films underwent much slower transformations than thicker ones. A model is proposed which explains the difference in transformation rates in terms of the physical constraint experienced by the film since grain growth in thinner films is limited by film thickness. Geometrical constraints imposed by trench and via structures appear to have an even greater retardation effect on the grain growth. Experimental observations indicate that it takes much longer for Cu in damascene structures to go through grain size transformations than blanket films.

Articles you may be interested inDefects introduced into electroplated Cu films during room-temperature recrystallization probed by a monoenergetic positron beam J. Appl. Phys. 98, 043504 (2005); 10.1063/1.2009813Seed layer dependence of room-temperature recrystallization in electroplated copper films

INTRODUCTIONCopper has ϳ40% lower electrical resistivity and about two orders of magnitude higher electromigration resistance than aluminum, 1,2 making it the metal of choice for high-performance interconnects at the 180-nm technology node and beyond. Understanding the relationship between interconnect metal microstructure and electrical properties can allow processing to be optimized to increase device yield and reliability. 3-6 This is particularly true for the electrochemically deposited Cu, the most practical and promising Cu deposition process for the current semiconductor industry.Electroplated Cu will undergo grain growth even at room temperature in blanket films and in damascene trenches due to the ample amount of interfa-cial energy stored in the as-plated, very fine initial grains, typically around 0.05 m or smaller. 7,8 Final grain size, crystal orientation, and Cu line tensile stress can be largely impacted by thermal cycles of subsequent processing. Earlier reports, by us and others, showed that the microstructure of Cu depended not only on anneal temperature, but also on temperature ramp rates and previous thermal processing. 6,9,10 The coefficient of thermal expansion (CTE) mismatch between Cu and the surrounding dielectric material makes the situation more complex. This CTE mismatch can cause large tensile stresses in the Cu lines and possible void formation, and via detachment, resulting in reliability issues, high line and via resistance, and low via chain yield. It is critical to understand the relationships between processing and microstructure, and the role of microstructure in determining device performance, yield, and reliability, in order to maximize the benefit of Cu metallization.The microstructures of Cu lines in damascene trenches annealed at temperatures from room temperature to 425°C using both rapid thermal processing (RTP) and furnace annealing were investigated using an array of characterization techniques including transmission electron microscopy (TEM), focused ion beam, scanning electron microscopy (SEM), and electron backscatter diffraction-orientation-imaging microscopy (EBSD-OIM). It was found that the final grain sizes strongly depend on the annealing process used; RTP generated larger grains than furnace annealing. The Cu line electrical resistance correlated with grain size differences observed for RTP and furnace anneals. The ramping rate, not the annealing time, played the critical role in the grain growth process. In either case, a high density of ⌺3 coincident site lattice (CSL) twin boundaries was observed in the Cu lines. Forty-five percent of the grain boundaries measured were found to be ⌺3 CSL twins, which are differentiated from random high-angle boundaries by having preferred electrical and diffusion properties. The minimum feature dimension of width or height of the damascene trenches limited the average grain size. Prior to the trench height limitation, the average grain size increased linearly with the trench width. The Cu (111) texture became stronger as th...

Copper electroplating has become the leading technology for gap fill of damascene structures on advanced interconnects. A key to developing a robust electroplating process that produces deposits free of voids and seams is understanding the role of the additive components, i.e., levelers, brighteners and wetting agents, and their relative diffusion/adsorption characteristics. Additionally, obtaining insight about the cathodic current/potential relationship is critical for maximizing the effectiveness of the additive components.Our results indicate that bath additive composition and the plating parameters (plating pulse frequency, and current density play critical roles in the outcome of the Cu fill. SEM cross sectional analysis of timed partial electroplating fill studies show two types of fill, 1) conformal and 2) bottom-up. Conformal fill of features smaller than 0.25 μm with an aspect ratio (AR) of 4.0 tends to form seam voids in the center of the structure. These seam voids can lead to early electromigration failures. On the other hand, bottom-up fill leads to a void free Cu deposit within the feature.