Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

Martino, M. D. V.; Martino, João Antônio; Agopian, Paula Ghedini Der; Vandooren, A.; Rooyackers, R.; Simoen, Eddy; Claeys, Cor

doi:10.1088/1361-6641/aa6764

Cited by 8 publications

(6 citation statements)

References 27 publications

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“…This channel length dependence is summed up by equation (1), published and explained in [32]. The introduced parameter m refers to the different drain current susceptibility to the effective values of channel length (L ef ), leading to different behaviors of differential pairs designed with each technology.…”

Section: Results and Analysismentioning

confidence: 99%

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Martino

Agopian

et al. 2018

Semicond. Sci. Technol.

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This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (A d), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest A d , while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trapassisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher A d and ON-state current than Point TFETs.

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Section: Results and Analysismentioning

confidence: 99%

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Martino

Agopian

et al. 2018

Semicond. Sci. Technol.

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“…I D -V G characteristics of p-type Ge/Si SPE-V-HTFET with and without HGD are supposed to be symmetric with their n-channel counterparts [24]. In Analog/mixed signal domain, the circuit-level performances are dependent on some device-level FOMs, such as cutoff frequency (f T ), maximum frequency of oscillation (f max ), intrinsic gain (A V ), and TGF which are already discussed in the earlier section consisting of RF performance analysis [16]. In the view of this, a basic current mirror circuit has been implemented in this sub-section.…”

Section: Circuit-level Performance Analysismentioning

confidence: 99%

“…Current mirror circuit is required to generate a replica of a reference current which corresponds to a current controlled current source. Out of several proposed topologies, we have considered the most basic and simple topology as shown in figure 12 [16] to verify circuitlevel performance of SPE Ge/Si heterojunction vertical TFET with and without HGD. We have considered a reference current of 100 nA for our analysis [25].…”

Section: Circuit-level Performance Analysismentioning

confidence: 99%

“…To reduce the ambipolar conduction in TFETs, a low-k gate dielectric is used at the drain end while at the source end a high-k gate dielectric is used to increase I ON [12]. The Ge/Si heterojunction TFETs (HTEFTs) obtained by replacing Si in the source region by the low band gap materials like Ge for the reduction of the tunneling barrier height for which the ONcurrent of the device getting enhanced [13][14][15][16]. Although III-V semiconductor based HTFETs [1,17] have attracted major attention of the researchers, but the Ge/Si HTFETs is no doubt a better choice over III-V HTFETs for modern integrated circuit (IC) technology because of better compatibility with the modern days CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

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Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET

Tripathy

Singh

Samad

et al. 2020

Semicond. Sci. Technol.

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This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC performance parameters in terms of ION/IOFF and subthreshold swing (SS) are investigated for the proposed V-HTFETs. The average SS for the proposed V-HTFET with an HGD is found to be as low as 20 mV dec−1 compared to V-HTFET without any HGD (26 mV dec−1) at VDS = 0.5 V. The proposed Ge/Si SPE-V-HTFET with an HGD possesses higher cut-off frequency of 502 GHz and maximum frequency of oscillation of 2.33 THz at VDS = 0.5 V over the Ge/Si SPE-V-HTFET without any HGD which possesses cut-off frequency of 273 GHz and maximum frequency of oscillation of 1.47 THz. The proposed Ge/Si SPE-V-HTFET with and without an HGD have then been used for designing a basic current mirror circuit. Device-level study has been carried out using SILVACO ATLASTM TCAD simulator while the circuit-level investigation has been performed using the look up table based Verilog-A models in the CADENCE Virtuoso tool. The performances of the Ge/Si SPE-V-HTFET with HGD based current mirror circuit is observed to be better than the corresponding current mirror circuit designed by Ge/Si SPE-V-HTFET without any HGD.

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“…In addition, because band-to-band tunneling (BTBT) is the main operation mechanism in TFETs, they can break the limitation of 60 mV/decade subthreshold swing (SS) in conventional MOSFETs, which relies on hot electron emission, especially at low voltages [7,8]. Finally, TFETs are more immune to short channel effects and temperature variations [9,10]. Therefore, these advantages make TFETs more favorable for circuits that are based on low-power applications.…”

Section: Introductionmentioning

confidence: 99%

Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance

et al. 2023

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In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO2 to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (Iamb). In contrast, the gate dielectric near the source region consists of high-k HfO2 to increase the on-state current (Ion) through the method of gate control. To further increase Ion, an n+-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large Ion of 7.79 × 10−5 A/μm, a suppressed Ioff of 8.16 × 10−18 A/μm, minimum subthreshold swing (SSmin) of 19 mV/dec, a cutoff frequency (fT) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications.

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Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

Cited by 8 publications

References 27 publications

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET

Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance

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