Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET

Abstract

This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC performance parameters in terms of ION/IOFF and subthreshold swing (SS) are investigated for the proposed V-HTFETs. The average SS for the proposed V-HTFET with an HGD is found to be as low as 20 mV dec−1 compared to V-HTFET without any HGD (26 mV dec−1) at VDS = 0.5 V. The proposed Ge/Si SPE-V-HTFET with an HGD possesses higher cut-off frequency of 502 GHz and maximum frequency of oscillation of 2.33 THz at VDS = 0.5 V over the Ge/Si SPE-V-HTFET without any HGD which possesses cut-off frequency of 273 GHz and maximum frequency of oscillation of 1.47 THz. The proposed Ge/Si SPE-V-HTFET with and without an HGD have then been used for designing a basic current mirror circuit. Device-level study has been carried out using SILVACO ATLASTM TCAD simulator while the circuit-level investigation has been performed using the look up table based Verilog-A models in the CADENCE Virtuoso tool. The performances of the Ge/Si SPE-V-HTFET with HGD based current mirror circuit is observed to be better than the corresponding current mirror circuit designed by Ge/Si SPE-V-HTFET without any HGD.

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance *

“…It has been established that the electrical characteristics of a device produced in this way are poor [31]. To counteract this effect, the buffer layer is placed midway between the ferroelectric layer and the silicon substrate [32][33][34][35]. Negative capacitance is a property of ferroelectric materials such as Si-doped HfO 2 that acts like a stepup transformer and increases the device's driving current and SS [36].…”

Dopingfree Schottky Buried Metal Layer Fully Depleted Planar FET for SCE Suppression at sub-28nm Technology Nodes

“…The cut-off frequencies were obtained using slope of -20dB/decade. Gain bandwidth product (GBP) represents the region of operation of FET for which the gain remains constant calculated for DC gain of 10 using gm 20πC gd [25]. Stable high frequency performance is observed in CP-BML FET as compared to JL-BML FET for which the GBP improves with scaling and at L g = 7nm is found to be 394 GHz for CP-BML FET.…”

Investigation of electrical parameters and temperature analysis of a dual-metal DG PNPN TFET with extended source

“…When used in low-power switching and analog/RF applications, the V TH , SS, and I OFF of a device should be low, while the I ON , I ON /I OFF , g m , f T , GBP, and other characteristics should be high. Compared to other architectures, the heavily doped pocket with PNPN structure provides a higher on current with a reduced SS as well as increased reliability [11,20,21]. To overcome the drawbacks of a single gate, such as threshold voltage, subthreshold swing (SS), and ON-current, a double gate TFET offers superior electrostatic control [22,23].…”

“…The electron velocity, on-state current, and consequently its transconductance, are improved with the use of dual material gate design. This work tried to boost the DC and analog/RF performance of conventional tunnel-FET, considering all these ideas [20][21][22][23][24][25][26][27][28][29][30][31].…”