21st International Conference on VLSI Design (VLSID 2008) 2008
DOI: 10.1109/vlsi.2008.73
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Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation

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Cited by 6 publications
(9 citation statements)
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“…Using moderately demanding delay and rise-time means and conservative standard-deviations chosen based on [19] and [20] ( -, -, , and ) a Monte Carlo simulation was run to show the histogram of the 1 dB flatness frequency and the max level resulting from the interaction of varying and simultaneously. The simulation is a statistical perturbation of the lowest 1 dB flatness point presented in Fig.…”
Section: A Rf Signal Generationmentioning
confidence: 99%
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“…Using moderately demanding delay and rise-time means and conservative standard-deviations chosen based on [19] and [20] ( -, -, , and ) a Monte Carlo simulation was run to show the histogram of the 1 dB flatness frequency and the max level resulting from the interaction of varying and simultaneously. The simulation is a statistical perturbation of the lowest 1 dB flatness point presented in Fig.…”
Section: A Rf Signal Generationmentioning
confidence: 99%
“…Stacking (6) for each of the MTSG levels yields the matrix shown in (20). A complex-valued LS regression is then performed to yield , , and .…”
Section: Computing Rf Performance Parametersmentioning
confidence: 99%
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