Analysis of Dont Care Bit Filling Techniques for Optimization of Compression and Scan Power

Abstract

Test power and test time have been the major issues for current scenario of VLSI testing. The test data compression is the well known method used to reduce the test time. The don't care bit filling method can be used for effective test data compression as well as reduction in scan power. In this paper we describe the algorithm for don't care assignment like MT(Minimum Transition)-fill technique and hamming distance based technique.The selective Huffman ,optimal Huffman and modified selective Huffman coding are applied on the mapping set to give the optimum Compression and weighted transition matrix is used for scan power Using these techniques find compression and scan power parameters like average power and peak power and conclude that MT-fill technique gives low peak and average powers and Hamming distance based modified selective Huffman coding technique gives higher compression ratio compare to another methods like selective and optimal Huffman coding.

Test Data Compression Using Variable Prefix Run Length (VPRL) Code

“…For example consider the test vector: 100XX011X11. This vector, after MT-fill [10] , would become 10000011111. If the test vector has a string of X bits that is not terminated by a non-X bit on the right side, then it should be filled by the bit value to the left of the sequence.…”

“…A series of X entries in the test vector are filled with the same value as the first non-X entry on the right side of this series [10]. This minimizes the number of transition in the test vector when it is scanned in.…”

“…0-fill, 1-fill and random fill are the techniques used previously. Later MT-fill and column wise bit filling [10,11] is used to fill the X bit which reduces the transition. The genetic algorithm based heuristic to fill the don"t cares is proposed in [21].…”

“…Among these, run length-based codes are used to encode the repeatedly occurring values and is an efficient method for test data compression. The don"t care bit filling methods [10] and test vector reordering [11] further enhances the test data compression. Thus, combining run length-based codes with the Bit filling [10] & reordering techniques [11], not only reduces the switching activity, but becomes efficient in increasing the test data compression.…”

“…There are many techniques to control the volume of test data, test application time and power consumption in test mode. Test data volume and power reduction can be achieved by utilizing Built-in-Self-test (BIST) [2,3], test data compaction or test data compression techniques [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][20][21][22]. However, BIST requires a longer test application time.…”