Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Abstract

Abstract. This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 µm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs

“…In this paper, we address to detect dynamic faults associated to resistive-open defects. In [14], dynamic faults associated to resistiveopen defects have been classified as follows: A cell is said to have an dynamic Read Destructive Fault (dRDF), if a write operation immediately followed by a read operation performed on the cell changes the logic state of this cell and returns an incorrect value on the output. Fig.…”

“…In general terms, a resistive-open defect is defined as a defect resistor between two circuit nodes that should be connected [3]. Moreover, this type of defect generally causes timing dependent faults, which means that a two-pattern sequence is usually necessary to sensitize theses faults [14]. According to [15], faults requiring more than one sequentially operation in order to be sensitized are called dynamic faults.…”

“…The evaluation of the proposed approach has been accomplished considering the BICS's fault detection capability and the leakage power consumption impact of the new BICS scheme on the SRAM's total power. In more detail, we have modeled the dynamic faults according to [14] and identified different values for the resistors able to generate the targeted faulty behavior. The effectiveness of the BICS proposed in this paper has been evaluated through electrical simulations based on 65nm technology library.…”

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

“…Many test approaches to detect memory faults have been proposed in literature. Strong, deterministic faults can be detected by schemes that rely on logic faults observation, such as March algorithms [4][5][6][7][8]. Yet, many of these algorithms do not target or have limitations detecting hard-to-detect faults.…”

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

“…Further, the distribution of such defects is directly correlated to the number of dynamic faults [4]. This defect generally causes timing dependent faults, which means that usually a 2-pattern sequence is necessary to sensitize it [5]. According to [4], faults requiring a large number of at-speed operations on each memory cell for sensitization are denominated dynamic faults.…”