DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Medeiros, Guilherme Cardoso; Taouil, Mottaqiallah; Fieback, Moritz; Poehls, Leticia Bolzani; Hamdioui, Said

doi:10.1109/ets.2019.8791517

Cited by 12 publications

(8 citation statements)

References 11 publications

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“…The parametric test solutions listed in Table VIII exemplify the versatility of parametric testing. On-chip voltage sensors (OCVSs) [25] focus on monitoring the voltage on the BLs when applying a BT sequence of read and write operations. A neighborhood-comparison logic circuit compares the measured voltage to a dynamic reference obtained through measurements from neighboring cells.…”

Section: B Previously Proposed Test Solutionsmentioning

confidence: 99%

“…A solution to reduce test escapes is using Designfor-Testability (DFT) circuits and stress tests. Examples of DFT methodologies that can enhance HTD faults' detection are schemes that perform memory operations differently [20][21][22] or schemes that monitor some parameters of the memory [23][24][25]. Even though there are different test solutions, it is still unclear if they can efficiently cover HTD faults.…”

Section: Introductionmentioning

confidence: 99%

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

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Manufacturing defects can cause Hard-to-Detect (HTD) faults in FinFET SRAMs. Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This paper presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

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Section: B Previously Proposed Test Solutionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

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“…Special DfT which can be used to complement March tests, can work better in detecting such faults. For example, the DfT proposed in [47] to detect HTD faults in SRAMs can be used here; it is based on monitoring the bit line swing at the input of the SA.…”

Section: Test Developmentmentioning

confidence: 99%

Testing Computation-in-Memory Architectures Based on Emerging Memories

Hamdioui

Fieback

Nagarajan

et al. 2019

2019 IEEE International Test Conference (ITC)

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Today's computing architectures and device technologies are becoming incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. Some of these are Computationin-Memory (CIM) architectures based on memristive devices; they integrate the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationin-memory bit-wise logical operations.

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“…These defects can be classified either as resistive-opens or resistive-bridge defects [4]. They can be classified as "weak" [5] if they are hard to detect, especially using traditional memory tests such as March tests [5]. Therefore, they may lead to test escapes, which might affect the FinFET device's susceptibility to single events due to ionizing particle strikes in the field, as discussed in this paper.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

et al. 2021

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Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

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DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Cited by 12 publications

References 11 publications

Hard-to-Detect Fault Analysis in FinFET SRAMs

Hard-to-Detect Fault Analysis in FinFET SRAMs

Testing Computation-in-Memory Architectures Based on Emerging Memories

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

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