Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Pathan, Ashfaque Ahmed; Memon, Tayab Din; Sohu, Fareesa; Rajput, Muhammad Awais

doi:10.52584/qrj.1901.12

Cited by 3 publications

(3 citation statements)

References 30 publications

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“…One of the latest methods of resource reduction in ASIC or or partially transformed to single-bit) [8][9][10][11][12][13][14][15], IIR filters [16][17][18], and some complex adaptive filter structures [19][20][21][22]. Other recent examples of SDM-based short word length systems include adaptive channel equalizers using a µless approach [23], Weiner filters [24], Matched filters [25], digital arithmetic units [26], smart sensor communications [27], correlation-less filters [28,29] and latest SDM-Based Image Processing [30].…”

Section: Introductionmentioning

confidence: 99%

A Novel Approach Toward Algorithm Architecture Co-Optimization for the Application of Adaptive Noise Cancellation for Wireless Communication

Pathan

2024

SJCMS

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As FPGA has been in trend for a few decades in prototyping simple to complex DSP systems, some issues are still highlighted in FPGA-based implementations. One issue is the limited resources mounted onboard. Optimization has always remained a choice of developers, either hardware or software-based. Algorithm architecture co-optimization is a domain that incorporates some changes in existing algorithms besides bringing some ways to produce compact architecture. One of the methods in architecture optimization is to use short-word length-based DSP systems that use a sigma-delta modulation (SDM) approach to reduce the actual data word length from multi-bit to single-bit. SDM in the design causes the system to become compact and efficient. This paper produces algorithm architecture co-optimization for the application of adaptive noise cancellers for wireless communication. The algorithm taken is SDM-based Steepest-Descent, and its implementation is compared with the new proposed SDM-based correlation-less design. Both approaches are simulated in MATLAB, and their functional verification is carried out along with comparing some statistical parameters, including SNR, MSE, and PE. Besides, both the designs are translated on Vertex-7 FPGA to verify the less resources consumed by the proposed method. The MATLAB and FPGA-based results indicate that the proposed design may be the best choice for less sensitive applications, like voice or video.

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Section: Introductionmentioning

confidence: 99%

A Novel Approach Toward Algorithm Architecture Co-Optimization for the Application of Adaptive Noise Cancellation for Wireless Communication

Pathan

2024

SJCMS

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“…Various SDM-based DSP applications for word length reduction and hence reducing the overall system complexity are reflected in the literature that includes but is not limited to simple arithmetic units [9][10][11], FIR filters (fully or partially transformed to single-bit) [12][13][14][15][16][17][18][19], IIR filters [20][21][22], and some complex adaptive filter structures [23][24][25][26]. Other recent examples of SDM-based short word length systems include adaptive channel equalizers using a µ-less approach [27], Weiner filters [28], Matched filters [29], digital arithmetic units [30], smart sensor communications [31], correlation-less filters [32,33] and latest SDM-Based Image Processing [34].…”

Section: Introductionmentioning

confidence: 99%

A novel approach toward optimized image processing using sigma delta modulation

Pathan,

Memon,

Aziz

et al. 2024

Mehran Univ. res. j. eng. technol.

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Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

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“…In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements [7,8]. The research proposes various traditional and nontraditional multiplier optimization methods and schemes and implements software based or on hardware (ASICS and FPGAs) [9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Computationally efficient low-power sigma delta modulation-based image processing algorithm

Pathan,

Memon,

Memon

et al. 2023

Mehran Univ. res. j. eng. technol.

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Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multi-bit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment.

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Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Cited by 3 publications

References 30 publications

A Novel Approach Toward Algorithm Architecture Co-Optimization for the Application of Adaptive Noise Cancellation for Wireless Communication

A Novel Approach Toward Algorithm Architecture Co-Optimization for the Application of Adaptive Noise Cancellation for Wireless Communication

A novel approach toward optimized image processing using sigma delta modulation

Computationally efficient low-power sigma delta modulation-based image processing algorithm

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