Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator [MOSFET applications]

Ohkura, Y.; Suzuki, Chikashi; Amakawa, H.; Nishi, Kenji

doi:10.1109/sispad.2003.1233639

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…Although gate leakage has been steadily increasing for the last few technology generations, the industry wide adoption of high-dielectric appears to stem this trend for the next few technology generations [16]. Consequently, the leakage current in a CMOS circuit is dominated by the subthreshold leakage .…”

Section: Leakage Power Uncertainty: Impact Of Pv Andmentioning

confidence: 99%

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs

Chakraborty

Roy

2012

IEEE Trans. VLSI Syst.

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Due to the inherent nature of heat flow in 3-D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The temperature of dies progressively increases with increasing distance from the heat sink. This heterogeneous temperature profile coupled with the strong dependence of leakage on temperature and process variation plays havoc in achieving system level energy efficiency in such systems, complicating the task of power provisioning in 3-D multicores. In this paper, we address this power provisioning challenge in 3-D ICs by advocating a novel stack aware microprocessor design paradigm, where the circuit designers are aware of the intended placement of a die in a 3-D stack. We present a concrete application of this paradigm through a stack aware threshold voltage ( ) assignment algorithm for a 3-D multicore system, where we specifically account for: 1) the change in the role of leakage power; 2) expected operating frequency; and 3) dependency of PV induced leakage variation and levels. Our stack aware scheme tunes assignment based on the vertical placement of the die in a 3-D stack. Detailed simulation based experiments with our proposed algorithm show 4%-19% improvement in energy efficiency for a typical multicore system organized as 3-D stacked dies.

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Section: Leakage Power Uncertainty: Impact Of Pv Andmentioning

confidence: 99%

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs

Chakraborty

Roy

2012

IEEE Trans. VLSI Syst.

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“…A coupled Monte Carlo-drift diffusion method [6] is employed in which Boltzmann transport equations for particles inside Monte Carlo 'window' region and current continuity equations outside 'window' region and Poisson equations are coupled self-consistently in arbitrary 2 or 3 dimensional device structure [1]. Gate injection and tunneling model [7] using the transfer matrix method are also included.…”

Section: Simulation Modelmentioning

confidence: 99%

A 3-dimensional particle device simulator; HyDeLEOSMC and its application to a FinFET

Ohkura¹,

Suzuki²,

Enda³

et al. 2005

2005 International Conference on Simulation of Semiconductor Processes and Devices

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“…Attempts to solve the BTE for the gate current problem were made [4,5]. An energy transport model and a Monte Carlo approach were successfully applied to gate current calculations for the case of hot carrier injection [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Study of Warm-Electron Injection in Double-Gate SONOS by Full-Band Monte Carlo Simulation

Giusi

Iannaccone

Mohamed

2008

IEEE Electron Device Lett.

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Abstract-In this letter, we investigate warm-electron injection in a double-gate SONOS memory by means of 2-D full-band Monte Carlo simulations of the Boltzmann transport equation. Electrons are accelerated in the channel by a drain-to-source voltage V DS smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based postprocessing method as a function of the particle distribution obtained from Monte Carlo simulation. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias, and warm-electron injection can be an interesting option for programming when short-channel effects prohibit the application of larger drain bias.Index Terms-FinFET memory, nonvolatile memory, SONOS.

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Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator [MOSFET applications]

Cited by 5 publications

References 9 publications

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs

A 3-dimensional particle device simulator; HyDeLEOSMC and its application to a FinFET

Study of Warm-Electron Injection in Double-Gate SONOS by Full-Band Monte Carlo Simulation

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