Analysis of hot-carrier-induced degradation mode on pMOSFET's

Matsuoka, F.; Hayashida, Hiroshi; Hama, K.; Toyoshima, Y.; Maeguchi, K.

doi:10.1109/16.106244

Cited by 60 publications

(12 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, in the present case, significant surface state generation (&), and large negative AVm, presumably caused by the surface state, are observed. Similar AIm vs V, results, but without significant AVm, is found in the literature [2].…”

Section: Hot Carrier Lifetime For Nmossupporting

confidence: 86%

0.15 μm CMOS with high reliability and performance

Takeuchi

Yamamoto

Tanabe

et al.

Proceedings of IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

show abstract

Section: Hot Carrier Lifetime For Nmossupporting

confidence: 86%

0.15 μm CMOS with high reliability and performance

Takeuchi

Yamamoto

Tanabe

et al.

Proceedings of IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

show abstract

“…stress is used to model the I d degradation caused by channel hot carriers because the damage is the result of channel hot-hole injection. 13,14) As seen in Fig. 3(b), the results of the model and data matched pretty well when A 2 ¼ 1:8 Â 10 7 , m 2 ¼ 1:09, and n 2 ¼ 0:32 are used in eq.…”

Section: Resultssupporting

confidence: 53%

The Impact of Gate-to-Source Tunneling Current on the Characterization of Metal-Oxide-Semiconductor Field-Effect Transistor's Hot-Carrier Reliability

Chen

Tsao

Ong

2003

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Drain current (I d) degradation due to Fowler-Nordheim (FN) stress and V g ¼ V d stress were investigated in 0.15 mm n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs). When pMOSFETs reach the lifetime under V g ¼ V d stress, the damage resulting from gate-tosource tunneling current is not negligible in comparison with the damage caused by channel hot carriers. I d degradation models of pMOSFETs under FN stress and V g ¼ V d stress were established. According to the I d degradation models, the impact of gate-to-source tunneling current on the result of hot-carrier reliability testing is discussed.

show abstract

“…In the past, few studies were conducted on the issues of widthdependent hot-carrier (HC) reliability, and few recent studies have been conducted [1]. The STI metal-oxide-semiconductor field-effect transistor (MOSFET), with a narrow channel width exhibiting server degradation after HC stress [1]- [3], was observed. For p-channel MOSFETs (pMOSFETs), the shrunk channel effect causing gate oxide damage near the recess is the dominant mechanism for the degradation of the drain current under the channel-HC (CHC) stress, also called the I G,max stress condition [1].…”

Section: Introductionmentioning

confidence: 98%

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

Wang

Hsieh

Liao

et al. 2011

IEEE Electron Device Lett.

View full text Add to dashboard Cite

The narrow-width W effect of metal-oxidesemiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δw affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δw, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δw, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage V TH , was obviously dominated by |Δw|/W, and the degradation of the narrow-width device was also increased for the wide width.Index Terms-Channel hot carrier (CHC), metal-oxidesemiconductor field-effect transistors (MOSFETs), narrow-width effect, shallow trench isolation (STI).

show abstract

Analysis of hot-carrier-induced degradation mode on pMOSFET's

Cited by 60 publications

References 19 publications

0.15 μm CMOS with high reliability and performance

0.15 μm CMOS with high reliability and performance

The Impact of Gate-to-Source Tunneling Current on the Characterization of Metal-Oxide-Semiconductor Field-Effect Transistor's Hot-Carrier Reliability

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

Contact Info

Product

Resources

About