Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Ortín-Obón, Marta; Gracia, Darío Suárez; Villarroya-Gaudó, María; Izu, Cruz; Viñals-Yúfera, Víctor

doi:10.1016/j.micpro.2016.01.005

Cited by 12 publications

(6 citation statements)

References 34 publications

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“…Therefore, using (6) and 7, we can write 2(T2-T4) < 2Ty-ω+1 (8) Based on (7) and (8), the odd inversion condition is obtained as…”

Section: Scheme-i: Algorithmmentioning

confidence: 99%

“…It brings about the decreases in number of transport advances with both PBI and MPBI coding are substantial. The execution of the proposed sub transport choice calculation for PBI coding is practically on a par with that of reenacted tempering in the transport progress lessening [6]. Multiprocessor framework on-chip (MPSoC) utilizes various CPUs alongside other equipment subsystem to actualize a system.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes

Kumari¹,

Prasad²

2017

IJET

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Due to rapid improvement for innovations in cryptography, the scattered of power link in connections of cryptography contexts instigates to resist through the power disseminated via substitute mechanisms of the communication subsystem, the switches and the sub modules of cutting edge encryption standard (AES). The dynamic power dissemination in joins is real supporter of the power utilization in organize on the chip. Due to self-exchanging and cross coupling capacitance the power consumption is shirking in communications system for security aspects. In the present research work the encoding strategy the key self-exchanging is diminish by examination the exchanging change and afterward the link between the connections is patterned and guaranteed that the power utilization is lessened. To upgrade control utilization in encryption and decoding process, Bit Encryption and Decryption Transition (BEDT) information schemes went for lessening the power disseminated by the AES chiefly include round key module in AES to perform XOR operation between 128 bits plain content and secrete key. The suggested research work in this paper is main basic concept of AES due to its number of round operations and also it will allow 39% of energy sprinkling and 9% of energy utilization without having more number execution debasement and with below 11% range overhead in the other cryptography frameworks. The proposed BEDT schemes depends on both odd modified and even rearranged, and after that sending the information to receiver that will performed utilizing the kind off reversal which lessens increasingly the exchanging movement. In these proposed three schemes, utilizes an easier decoder while accomplishing a higher movement diminishment. In the prior schemes, the quantity of changes from 0 to 1 for two back to back flutters is tallied. The bit transitions reduce the number of transitions before transmitting the data to decryption.

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“…Therefore, using (6) and 7, we can write 2(T2-T4) < 2Ty-ω+1 (8) Based on (7) and (8), the odd inversion condition is obtained as…”

Section: Scheme-i: Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes

Kumari¹,

Prasad²

2017

IJET

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“…Different ONoC topologies, e.g., mesh, torus, clos and fat tree use 4-port or 5-port optical routers with one core attached to each router. A topology that has two cores attached to a single router has been proposed to form a cluster [33,34]. Cluster-based topology saves chip area and requires a 6-port optical router for the additional core connected to the same router.…”

Section: Introductionmentioning

confidence: 99%

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Yahya

Gao

et al. 2019

Electronics

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Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

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“…NoCs have found varying applications such as image and signal processing [1], multiprocessor systems [9], and virtual machine implementations [10]. Based on how the switches are interconnected, there are different NoC topologies such as mesh, torus, tree, ring, star, and BFT, as shown in Figure 1 [11]. In a mesh topology, every switch, except the ones on the edges, is connected to 4 other neighboring switches.…”

Section: Introductionmentioning

confidence: 99%

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

Vipin

2019

International Journal of Reconfigurable Computing

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Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees are proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node. This scheme is very efficient in interconnected networks such as computer networks, which use generic switches for interconnection. In an NoC context, especially for field programmable gate arrays (FPGAs), fat trees require more complex switches as we move higher in the hierarchy. This restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through using fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by varying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch architecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this architecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.

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Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Cited by 12 publications

References 34 publications

Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes

Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

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