Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs

Abstract

Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-uniform temperature profiles that exist along their lengths, which in turn arise due to the thermal gradients in the underlying substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed for the first time. The model has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.

Temperature-Aware Design and Management for 3D Multi-Core Architectures

“…These temperatures lead to accelerated degradation rates in various thermally-induced parametric factors [31] (cf. Section 1.3), such as electro-migration (EM) [30], biastemperature instability (BTI) [24], gate oxide breakdown [29], propagation delays [57,58], leakage power [59], and power/ground integrity [31]. Thus, it is crucial to design these high-power density MPSoCs in a thermally-aware manner to abate the mentioned degradation factors, even before experiencing the non-homogenous time-varying workload characterizations.…”

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

“…This is necessary mainly due to the fact that non-uniform interconnect temperature has an unavoidable impact on the wire planning. More specifically, the non-uniform temperature profile along the interconnect line can severely affect the clock skew and this effect cannot be addressed by simply accounting for a uniform worst-case maximum temperature along the interconnect length [20]. As an example, consider having exponential temperature distributions along the interconnect length.…”

“…Clearly, the dependence of interconnect performance on non-uniform temperature distributions along the length of global wires will have a big impact on the solutions to many physical design and layout optimization problems, including clock skew control, wire sizing, layer assignment, crosstalk effects, and buffer insertion. These observations suggests that non-uniform temperature profiles along the interconnect lines should be considered during the design optimization flow and proper steps should be taken to ensure the optimal performance [20]. It should be noted that the effects of such thermal gradients on the performances of devices are also very important and perhaps more severe than such effects on the interconnect performance.…”

An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

“…The regions with higher temperature are commonly referred to as hot-spots. Hot-spots simultaneously lead to temperature gradients that affect performance [2] (including delay and timing) and reliability among a host of other issues, and also result in a general over-design in highperformance microprocessor packaging and cooling solutions. These thermal problems have now been identified and projected as major challenges for future IC design by leading semiconductor manufacturers and by the International Technology Roadmap for Semiconductors (ITRS) [3].…”