Analysis of on-chip inductance effects for distributed RLC interconnects

Abstract

This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization technique for distributed interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. On the other hand, for scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues has also been analyzed.

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

“…15, we need to derivate the total transmission parameter matrix. Using the ABCD transmission parameter matrix for a uniform RLC transmission line of length ℓ as given in [45]- [47], we can express the total ABCD transmission parameter matrix of the configuration in Fig. 15 as…”

Transfer Function and Compact Distributed RLC Models of Carbon Nanotube Bundle Interconnets and Their Applications

“…It is also known that as the transfer function of an on-chip interconnect in the Laplace domain is obtained, its inductance effects, transferred signal stability, and output response excited by an arbitrary signal can be determined accurately [20]. The fourthorder approximation is often used in the derivation of transfer function.…”

On-chip data communication : analysis, optimization and circuit design

“…Note that the driver impedance is set at zero Ohm, to show the idealized situation. In actual applications, short wires are likely to get small drivers, creating a relatively high driver impedance and dampening the transmission-line effects to some degree [40]. Because inductance can cause ringing and other detrimental effects, its presence is sometimes even seen as a disadvantage [24,40].…”

“…In actual applications, short wires are likely to get small drivers, creating a relatively high driver impedance and dampening the transmission-line effects to some degree [40]. Because inductance can cause ringing and other detrimental effects, its presence is sometimes even seen as a disadvantage [24,40]. The fact that inductance, in combination with capacitance, also creates propagation delay does not help to make it a favorable property.…”

“…One often used improvement incorporates the inductance into the model for delay [40,55,56]. As was discussed in section 3.5.2, the inductance does limit the propagation velocity, so in some cases it can be beneficial to include it, as RC models can predict physically impossible delays that would require propagation velocities larger than the speed of light.…”