Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Abstract

This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in the driver capacitance and output resistance with scaling makes deep submicron (DSM) designs increasingly susceptible to inductance effects. Also, the impact of inductance variations on performance has been quantified. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues have been analyzed.

A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation

“…However, computing the response in the time domain is analytically intractable. The above transfer function is therefore approximated by a second order Padé approximation as (2) where The 50% delay is given by This transfer function can be used to calculate the 50% delay [16]. Long VLSI interconnects are typically broken up into buffered segment of equal lengths and driven by identical repeaters.…”

“…For minimum total delay in these long interconnects, the delay per unit length in the optimally buffered segment should be minimized. The driver size and interconnect length can be numerically optimized to give minimum delay per unit length [16], [17].…”

“…The second order transfer function given by (2) and discussed in [16], [17] can be critically damped, overdamped, and underdamped when is equal to, greater than, or less than zero respectively. The response of an overdamped system is very similar to an RC line whereas for an underdamped system, the behavior is significantly different from an RC line, i.e., inductive effects are significant.…”

“…The response of an overdamped system is very similar to an RC line whereas for an underdamped system, the behavior is significantly different from an RC line, i.e., inductive effects are significant. Since and are functions of and and is a function of , it has been shown [16] that for optimum values of and where interconnect delay is minimum for a given line inductance, a value can be obtained for which the system will be critically damped [16]. If line inductance is less than , the system will be overdamped where as if line inductance is greater than , the system will be underdamped, as specificed in the second equation shown at the top of the page.…”

Inductance aware interconnect scaling

“…Using the ABCD parameters of a uniform distributed RLC line, It can be shown that the input-output transfer function can be approximated by a second order transfer function as discussed in [5]. ( 1) where…”