Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits

Vichienchom, Kasin; Liu, Wentai

doi:10.1109/iscas.2003.1205639

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…Over the past years, the rapid development of high speed data communication reveals the importance of clock and data recovery circuits. With wide applications in a lot of areas, clock and data recovery circuits are gaining more and more popularity among researchers [1][2][3][4][5][6][7][8] [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. As hinted by its name, the circuit can extract a clock signal and use this clock signal to recover the data.…”

Section: Introductionmentioning

confidence: 99%

“…Clock and data recovery circuit performance management is increasingly important due to the explosive development of high speed communication systems. During the past years, extensive research has been done to investigate the clock and data recovery circuit [1][2][3][4][5][6][7][8] [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. Specifically, the existing results mainly fall into three categories: clock and data recovery circuit design and implementation [1][2][3][4][5][6][7][8] [11][12][13], clock and data recovery circuit mathematical model investigation [14][15][16][17], and testing schemes for clock and data recovery circuits [18][19][20]…”

Section: Introduction and Designmentioning

confidence: 99%

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Performance Analysis for Clock and Data Recovery Circuits under Process Variation

Pan

Jone

Das

2008

2008 IEEE Instrumentation and Measurement Technology Conference

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Clock and data recovery circuits play a very important role in modern data communication systems. It has very wide application in many areas, such as optical communications and interconnection between chips [1]. Today in IC industry, the shrinkage of feature size increasingly enlarges the uncertainty of circuit performance caused by process variation. As the data transmission speed dramatically increases, this uncertainty will heavily affect the clock and data recovery circuit performance and reliability in communication systems. Thus, research on performance variation of a clock and data recovery circuit caused by process variation is meaningful. The conclusion will have significant influence on chip testing. Firstly and most importantly, I am very grateful to my advisor, Dr. Wen-Ben Jone, for his valuable guidance and encouragement. Without him, I could not have worked on this research smoothly. For this research, his time and efforts deserve the most credit. Secondly, I would love to thank Dr. Carter and Dr. Vemuri for their time, instruction and guidance in my research. Thirdly, I really appreciate all the love and support from my husband, Andrew Gilmore, from my grandparents, my parents and sister-Ms. Ruizhen He, Mr. Ye Chen, Ms. Xiuqun Huang, Mr. Zhuoyu Pan, Ms. Liming Pan, and from my parents-in-law, Mr. and Mrs. Gilmore. Last, I really appreciate all the help and support from my good friends who are willing to give me a hand to help me proceed in my research and life-Abelardo, Weihuang, Tao and Rui.

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Section: Introductionmentioning

confidence: 99%

Section: Introduction and Designmentioning

confidence: 99%

Performance Analysis for Clock and Data Recovery Circuits under Process Variation

Pan

Jone

Das

2008

2008 IEEE Instrumentation and Measurement Technology Conference

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“…However, since the phase error information of a bang-bang phase detector is one-bit, this kind of timing recovery circuits usually has a long acquisition time and suffers large phase jitter [2]. M.…”

mentioning

confidence: 99%

An Improved Digital Timing Recovery Circuit for Burst-Mode Communications

Liu

Guo

Song

et al. 2006

2006 International Conference on Wireless Communications, Networking and Mobile Computing

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Burst-mode communication (or burst-mode transmission) has been increasingly adopted in modern wireless communication systems. It requires a digital timing recovery circuit with short acquisition time. The bang-bang phase detector is widely used in digital timing recovery circuits owing to its simple structure. However, these timing recovery circuits do not provide a quick acquisition. In this paper, an enhanced bang-bang phase detector is proposed, increasing the resolution of the timing error by over-sampling the data L times and therefore reducing the phase error variance by 1/L 2 times. This timing recovery scheme can be implemented using a Direct Digital Synchronizer (DDS). Both simulation and experimental results illustrate that the new scheme has a shorter acquisition time and a longer holding time, satisfying the need of burst-mode communications. Keywords: Burst-mode communication, bang-bang phase detector, phase lock loop (PLL), acquisition time1．Introduction Timing recovery circuit is an essential part of digital communication receivers. Bang-bang phase detector is a common structure adopted in various timing recovery circuits. Conventional bang-bang phase detector samples the NRZ input at a clock which is two times of the symbol rate and calculates the phase error signal by logic operations [1]. It has been widely used in optical receivers due to its simple structure and high processing speed. However, since the phase error information of a bang-bang phase detector is one-bit, this kind of timing recovery circuits usually has a long acquisition time and suffers large phase jitter [2]. M. Ramezaizi proposed an improved bang-bang phase detector for the optical receivers with four samples in one clock period by an analog phase shifter, and hence it generates two-bit phase error information by each operation [3]. The advantage obtained from the analog phase shifter is limited because the number of quantization steps is 4 (merely two-bit phase error information). Burst-mode transmission is a popular modulation technique used in wireless communication systems, such as in satellite communication, TDMA systems and military communication systems. In burst-mode communications, the timing recovery circuit requires a quick acquisition and long holding time. It is apparent that neither the original bang-bang phase detector nor the M-R improved scheme meets this requirement. Here, we propose an enhanced bang-bang phase detector to address these issues. This method increases the phase error information precision by over sampling the input data L times and provides a linear characteristic curve of the phase detection. The implementation of the resulting timing recovery circuit is consist of a direct digital synchronizer (DDS) and a digital loop filter. The DDS can fully utilize the phase error

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“…The NXO PD circuits have a better acquisition performance and less output jitter [39]. Oversampling PDs are discussed in Chapter 4.…”

Section: Multi-phase and Multi-bit Phase Detectorsmentioning

confidence: 99%

All-digital clock and data recovery architectures

Ahmed¹

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Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits

Cited by 4 publications

References 4 publications

Performance Analysis for Clock and Data Recovery Circuits under Process Variation

Performance Analysis for Clock and Data Recovery Circuits under Process Variation

An Improved Digital Timing Recovery Circuit for Burst-Mode Communications

All-digital clock and data recovery architectures

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