Analysis of Self-Heating Effects in Multi-Nanosheet FET Considering Bottom Isolation and Package Options

Investigation of Optimal Architecture of MoS2 Channel Field-Effect Transistors on a Sub-2 nm Process Node

“…For the thermal characterization, the supply voltage was set to 0.7 V, the same conditions as in the previous subsection where we analyzed the electrical characteristics and the ambient temperature ( T Air ) to 300 K. Δ T , which is an increased temperature compared to the ambient temperature ( T Air ), increases in proportion to the thermal resistance, R th , by the power consumed in the channel of the MoS 2 -FETs. As reported in previous studies, , the lattice temperature including the self-heating effect ( T LATTICE = T Air + △ T ) varies depending on the packaging type, and in this work, a flip-chip package type with a solder or a gold bump is assumed. The flip-chip package is a package type with the shortest path from chip devices to circuit boards, so it is known that high-speed operation is possible due to low-resistance components and noise.…”

“…In other words, it can be confirmed that a transistor with a complex 3D structure introduced with the expectation of a decrease in R has a risk of an increase in C. In addition, the complex transistor structure at the nanoscale process node also affects the mass production yield and thermal issues. 24 Therefore, the introduction of a new channel material besides the introduction of such a complex monolithic 3D structure at the sub-2 nm process node is attracting attention as one of the breakthroughs. Two-dimensional TMDC materials have recently been attracting attention as a beyond-silicon technology because they have superior interface properties and high mobility properties due to van der Waals bonding compared to silicon.…”

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

“…In case of the OTA, AC simulation was performed from 100 Hz to 1000 MHz in units of decades. Transistor sizing was adjusted in a ratio of M 1,2 :M 3,4 :M 5 :M 6 =5:10:2:1, and it was designed with a load capacitance of 100 fF and a reference current of 70 µA [27], [32]. In case of the 4-bit ALU, transient simulation was performed from 0 to 500 ps.…”

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

“…Therefore, the heat generated by the structure cannot be dissipated. The heat generation is called by the self-heating effect (SHE) cause lowering the mobility of carriers by phonon scattering [10][11][12][13][14]. In addition to this, SHE causes hot carrier injection and bias temperature stability to lower device reliability [15,16].…”