Analysis of snapback behavior on the ESD capability of sub-0.20 μm NMOS

Amerasekera, A.; Gupta, Vikas; Vasanth, K.; Ramaswamy, S.

doi:10.1109/relphy.1999.761608

Cited by 20 publications

(13 citation statements)

References 8 publications

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“…Both kinds of ESD devices have the same TLP thermal runaway current about 3.5 A. The thermal failure threshold is expected to occur at a specific temperature Tcrit for a given device, and can be expressed as (1) is stated in [12].…”

Section: Esd Testing Resultsmentioning

confidence: 99%

Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors

Huang

Chen

2011

IEICE Trans. Fundamentals

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The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggeringon voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turningon mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 μm process, such as 0.5 μm and 1 μm, ESD designers can use pickup insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 μm and newer processes, such as 0.15 μm, 0.13 μm, 90 nm, etc., ESD designers must use non-pickup insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pickup insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low turn-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pickup insertion cascode NMOS transistor's turning on resistance is smaller than the pickup insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pickup insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pickup insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.

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Section: Esd Testing Resultsmentioning

confidence: 99%

Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors

Huang

Chen

2011

IEICE Trans. Fundamentals

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“…Even for larger spacing, the results were identical to those reported in Figure 3. Given the relation between β NPN and M [14], this implies that the high current β NPN has to be very low (<1).…”

Section: Introductionmentioning

confidence: 99%

Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

Boselli

Vassilev

Duvvury

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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“…It is due to both the gate oxide breakdown and junction-degradationrelated problems, caused by the decreased oxide thickness and increasing doping levels in scaled technologies [5]. The ESD problems are further aggravated by the tight design window for high-performance I/O circuits, not allowing large ESD devices to be used as protection elements [6].…”

mentioning

confidence: 99%

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

Shrivastava

Baghini

Gossner

et al. 2010

IEEE Trans. Electron Devices

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Abstract-In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.Index Terms-Drain-extended MOS (DeMOS), hot carrier, input/output, lightly doped drain MOS (LDDMOS), mixed signal, reduced surface field (RESURF), reliability.

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Analysis of snapback behavior on the ESD capability of sub-0.20 μm NMOS

Cited by 20 publications

References 8 publications

Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors

Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors

Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

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