Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

Abstract

PURPOSEIn this work the high current behavior of Drain-Extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology will be investigated. It will be shown that a sufficient level of ESD robustness (I T2~2 mA/μm) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections. [

Novel devices in ESD protection

“…In all cases the common finding is a low ESD hardness for the grounded gate DeMOS configuration. Recently an It2 of 0.1mA/µm was reported for a 65 nm CMOS technology [12]. The failure analysis has shown a melting funnel from drain to source similar to the failure picture of fully silicided CMOS devices [13].…”

“…By construction a DeMOS is an asymmetric device. Applying the high current pulse to the 'source' leads to It2 values of 8 mA/µm, almost two order of magnitude higher than stressing the 'drain' [12]. This has been explained by the lower emitter efficiency of in the swapped contact configuration [12].…”

“…Applying the high current pulse to the 'source' leads to It2 values of 8 mA/µm, almost two order of magnitude higher than stressing the 'drain' [12]. This has been explained by the lower emitter efficiency of in the swapped contact configuration [12]. Of course, this is not an option to be used in circuit applications due to the low breakdown voltage which interferes with normal operation.…”

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

“…Furthermore, the optimization for ESD robustness in these works [9], [10] means giving up on R ON , which again leads to a tradeoff between ESD robustness and the device's nominal operation. Work reported in [11] shows improved ESD robustness of DeNMOS devices by using gate and substrate biasing, whereas the proposed ESD protection implementation does not provide an ESD robust I/O driver. The DeNMOS device is still prone to failure when used as an I/O driver (specifically output driver).…”

On the differences between 3D filamentation and failure of N & P type drain extended MOS devices under ESD condition

“…Low Voltage (LV) NMOS device is widely used as a ESD clamp because of its high failure current value (I T2 ), whereas the Drain extended NMOS (DeNMOS) devices have been found to be extremely vulnerable towards the ESD event [1]- [4]. Recently we presented a complete picture of STI type DeNMOS device failure and current filamentation using Transient Interferometric Mapping (TIM) experiments and 3D TCAD simulations [5] [6].…”