2010
DOI: 10.1109/ted.2010.2055276
|View full text |Cite
|
Sign up to set email alerts
|

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

Abstract: Abstract-We present experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metal-oxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions. Physical insight toward pulse-to-pulse instability is given. Both the current (I TLP ) and time evolution of various events such as junction breakdown, parasitic bipolar triggering, and the base push-out effect are discussed in detail. Differences between the 2-D and 3-D simulation (m… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2010
2010
2023
2023

Publication Types

Select...
6
1

Relationship

1
6

Authors

Journals

citations
Cited by 22 publications
(3 citation statements)
references
References 16 publications
0
3
0
Order By: Relevance
“…In Part I [10], we have also seen (Fig. 5) improvement in failure threshold by extending n + drain diffusion (DL = 2.2 μm) and drain contact (no change in ballast resistance) all over the drain diffusion.…”
Section: Further Improvement In Failure Thresholdmentioning
confidence: 69%
See 1 more Smart Citation
“…In Part I [10], we have also seen (Fig. 5) improvement in failure threshold by extending n + drain diffusion (DL = 2.2 μm) and drain contact (no change in ballast resistance) all over the drain diffusion.…”
Section: Further Improvement In Failure Thresholdmentioning
confidence: 69%
“…5 shows the (a) current density, (b) electric field, and (c) impact ionization contours for a modified device (DL = 2.2 μm) at a higher TLP current (i.e., 2 mA/μm). The modified device fails at 2.5 mA/μm [10], whereas, from Fig. 5, an efficient bipolar triggering is evident, without any device failure.…”
Section: Further Improvement In Failure Thresholdmentioning
confidence: 86%
“…Since the thermal diffusion length of silicon devices for 100 ns ESD simulation is approximately 3 μm, the substrate thickness T Sub is chosen to be 3 μm. (15) All the four terminals, namely, the substrate, source, drain, and gate, are used as a heat sink. The surrounding temperature of the device is set as 300 K.…”
Section: Esd Protection Tfet and Networkmentioning
confidence: 99%