Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

Shrivastava, Mayank; Gossner, Harald; Baghini, Maryam Shojaei; Rao, V. Ramgopal

doi:10.1109/ted.2010.2055278

Cited by 31 publications

(4 citation statements)

References 9 publications

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“…This is because the current at failure is not uniformly distributed across the entire width of the device, but rather is limited to a narrow current filament. The reader is referred to Shrivastava [18] for a detailed description of how such current filaments develop and the mechanisms underpinning it. One of the key mechanisms is the localized triggering of the parasitic bipolar.…”

Section: B 25ns Measurement and Resultsmentioning

confidence: 99%

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

Toner¹,

Eisenbrandt

Frank

et al. 2021

IEEE J. Electron Devices Soc.

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A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific onresistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

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Section: B 25ns Measurement and Resultsmentioning

confidence: 99%

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

Toner¹,

Eisenbrandt

Frank

et al. 2021

IEEE J. Electron Devices Soc.

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“…The I -V measurements are taken up to the failure point, to quantify the failure current for different duration ESD events. The device fails due to current filamentation and thermal runaway [34], effects not readily captured in a compact model; however, the usual purpose of ESD circuit simulation is to check whether all the devices remain biased within safe limits rather than to simulate the dynamics of failure. Pulse I -V data show that the ON-resistance of a protection device increases with pulsewidth and current density; this is a consequence of Joule heating in the device series resistance.…”

Section: A Transmission Line Pulse Testingmentioning

confidence: 99%

Compact Models for Simulation of On-Chip ESD Protection Networks

Rosenbaum,

Huang,

Drallmeier

et al. 2024

IEEE Trans. Electron Devices

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Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design's ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.

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“…An ideal current source (defined pulse shape) is used as the stress stimulus during electrothermal TCAD simulations with proper electrical and thermal contacts. The 3-D TCAD simulation approach is borrowed from our previous works [2], [4]. Various physical models are included to capture high field and high current effects, such as avalanche action, carrier recombination (Shockley-Read-Hall (SRH) and auger), and electric field-dependent mobility degradation models.…”

Section: Understanding the Root Cause Of Failurementioning

confidence: 99%

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

Kranthi

Sarro

Sankaralingam

et al. 2021

IEEE Trans. Electron Devices

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A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure. Index Terms-Current filaments, drain-extended nMOS [laterally double diffused MOS (LDMOS)], electrostatic discharge (ESD), International Electrotechnical Commission (IEC), system-level ESD. I. INTRODUCTIONT HE electrostatic discharge (ESD) protection design is particularly challenging in automotive applications because product requirements often dictate qualification for a variety of stress models in addition to human body model (HBM) and charge device model (CDM). For example, the communication Manuscript

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Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

Cited by 31 publications

References 9 publications

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

Compact Models for Simulation of On-Chip ESD Protection Networks

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

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