No abstract

No abstract

No abstract

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific onresistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Tomorrow's power electronic systems require cost-saving and more efficient power conversion solutions. The heterogeneous integration of GaN-based high electron mobility transistors (HEMTs) together with silicon CMOS by micro-Transfer-Printing could be a key technology for this. It enables the integration of highly integrated mature CMOS logic functionality with fast GaN HEMT output drivers with very low on-state and switching losses. The scalability by design measures of the printed HEMT is investigated in terms of drain-to-gate spacing and channel width defining breakdown voltage and area-related parameters like on-resistance. The design flexibility of the micro-Transfer-Printing by printing the HEMTs on top of the CMOS devices without restrictive design rule limits is investigated by CMOS DC parameter comparison and thermal TCAD Design OfExperiment (DOE) study. No electrical or thermal functional limitation of printing the HEMTs directly on top of the CMOS dielectric layer stack was found. This enables the usage of the isolation capabilities of the CMOS dielectric layer stack to enhance the HEMT breakdown voltage.