Heterogeneous Integration of Microscale Gallium Nitride Transistors by Micro-Transfer-Printing

Lerner, Ralf; Eisenbrandt, Stefan; Bonafede, Salvatore; Meitl, Matthew A.; Fecioru, Alin; Trindade, António Jośe; Reiner, Richard; Waltreit, Patrick; Bower, Christopher A.

doi:10.1109/ectc.2016.373

Cited by 11 publications

(6 citation statements)

References 13 publications

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“…This flow is shown in Figure 4. [24], [25], [26]. Additional processing is needed for release, printing and interconnect.…”

Section: Micro-transfer-printing Gan On Cmosmentioning

confidence: 99%

“…The devices are printed to a Si CMOS wafer and then interconnected using Cu RDL traces. [24] Around the chiplets additional area is required in both x and y directions for the release trenches, typically these are designed with a width of 10microns. In one direction non under-etched area is used to form the anchor regions (Figure 5b).…”

Section: Micro-transfer-printing Gan On Cmosmentioning

confidence: 99%

“…(c) The devices are retrieved with an elastomer stamp. (d)The devices are printed to a Si CMOS wafer and then interconnected using Cu RDL traces [24].…”

mentioning

confidence: 99%

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Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Lerner¹,

Hansen²

2021

ISPS'21 Proceedings

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Several approaches for close integration of power switches with CMOS logic are subject of technical evaluations and academic discussions. This paper identifies the commercially relevant processing steps of different integration methods (HV and SOI CMOS, monolithic integration in SOI and in GaN, Direct Wafer Bonding, micro-Transfer-Printing of GaN on CMOS and CMOS on GaN) and compares them on simple cost per wafer and cost per chip models. Four examples of real ICs verify the simple costs per chip model. Commercially attractive high voltage to logic partitionings are identified for the different integration approaches.

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“…This flow is shown in Figure 4. [24], [25], [26]. Additional processing is needed for release, printing and interconnect.…”

Section: Micro-transfer-printing Gan On Cmosmentioning

confidence: 99%

Section: Micro-transfer-printing Gan On Cmosmentioning

confidence: 99%

See 1 more Smart Citation

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Lerner¹,

Hansen²

2021

ISPS'21 Proceedings

Self Cite

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“…1). To illustrate and to solve this co-design problem, we exemplarily utilize a promising new assembly technology called micro-transfer printing (µTP) [4]- [7].…”

Section: Imentioning

confidence: 99%

Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer Printing

Fischbach

Horst

Lienig

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Technologies for heterogeneous integration have been promoted as an option to drive innovation in the semiconductor industry. However, adoption by designers is lagging behind and market shares are still low. Alongside the lack of appropriate design tools, high manufacturing costs are one of the main reasons. Micro-transfer printing (µTP) is a novel and promising micro-assembly technology that enables the heterogeneous integration of dies originating from different wafers. This technology uses an elastomer stamp to transfer dies in parallel from source wafers to their target positions, indicating a high potential for reducing manufacturing time and cost. In order to achieve the latter, the geometrical interdependencies between source, target and stamp and the resulting wafer utilization must be considered during design. We propose an approach to evaluate a given µTP design with regard to the manufacturing costs. We achieve this by developing a model that integrates characteristics of the assembly process into the cost function of the design. Our approach can be used as a template how to tackle other assemblyrelated co-design issues-addressing an increasingly severe cost optimization problem of heterogeneous systems design. Index Terms-assembly-related chip/package co-design, heterogeneous integration on package-level, micro-transfer printing, economical cost function, manufacturing costs, wafer utilization, maximum independent set problem.

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“…The source wafer can carry different components (such as passive or active devices), referred to as source dies, to be integrated into a heterogeneous system. In order to release the dies from the source wafer, wet chemical undercut etching is performed prior to the actual transfer process [8], [9]. The target wafer comprises the target dies on which the source dies shall be printed.…”

Section: M -T Pmentioning

confidence: 99%

A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems

Fischbach

Horst

Lienig

2019

2019 International 3D Systems Integration Conference (3DIC)

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Micro-transfer printing (µTP) is a promising assembly technology that enables heterogeneous integration of dies originating from different wafers. It combines the advantages of pick-and-place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. µTP applies an elastomer stamp to transfer multiple dies from source to target wafers in parallel. Increasing the stamp size allows for the transfer of more dies at once and reciprocally shortens the manufacturing time, enabling extensive cost reductions. On the other hand, larger stamps result in a lower wafer utilization, thereby causing increases in costs. Finding the cost-optimal stamp layout is one of the key tasks when designing heterogeneous systems for µTP. There is no trivial solution to calculate the wafer utilization needed to evaluate the quality of a stamp layout. Based on a graph problem known as maximum independent set, we propose a model to determine the wafer utilization subject to the stamp and wafer layout. We demonstrate the application of our model within an economic cost function to optimize a µTP design with regard to manufacturing costs.

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Heterogeneous Integration of Microscale Gallium Nitride Transistors by Micro-Transfer-Printing

Cited by 11 publications

References 13 publications

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer Printing

A Graph-Based Model of Micro-Transfer Printing for Cost-Optimized Heterogeneous 2.5D Systems

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