We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results. [Keywords: Electrostatic discharge (ESD), Silicon Controlled Rectifier (SCR), ESD protection circuits. ]

We compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout. The devices are evaluated using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current. We also report that SCR turn-on time is highly dependent on the amplitude of the applied pulse.

A scalable, compact model for SCR-based ESD-protection devices, which can simulate transient voltage overshoots observed on the timescale of charged device model (CDM) events, is presented. This model captures the effect that layout spacings have on SCR characteristics such as holding voltage and trigger current. Bias and time dependencies of SCR on-resistance are captured with a resistance model that accounts for self-heating and velocity saturation. [Keywords: Electrostatic discharge (ESD), silicon controller rectifier (SCR), compact modeling.]

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure. Index Terms-Current filaments, drain-extended nMOS [laterally double diffused MOS (LDMOS)], electrostatic discharge (ESD), International Electrotechnical Commission (IEC), system-level ESD. I. INTRODUCTIONT HE electrostatic discharge (ESD) protection design is particularly challenging in automotive applications because product requirements often dictate qualification for a variety of stress models in addition to human body model (HBM) and charge device model (CDM). For example, the communication Manuscript