Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

Abstract

We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results. [Keywords: Electrostatic discharge (ESD), Silicon Controlled Rectifier (SCR), ESD protection circuits. ]

Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

“…The SCR 1530-4388/$26.00 © 2011 IEEE anode-to-cathode spacing (S ac ) was fixed at the minimum value allowed by the layout design rules, which is 0.36 μm, so as to minimize the intrinsic turn-on delay of the SCR [4].…”

“…For example, the structure in [2] utilizes a dummy-gate structure to improve the turn-on speed of the SCR device. Among the various SCR-based ESD protection designs, the diode-triggered SCR (DTSCR) prevails in advanced CMOS technologies due to its design simplicity [3], [4]. When SCR-based protection devices are subject to nanosecond-scale discharges, such as charged device model (CDM) ESD, they are often unable to clamp the pad voltage below the breakdown voltage of thin gate oxides, particularly in sub-100-nm CMOS technologies [5]- [10].…”

Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

“…The delay for the emitter current to set up corresponds to the time required for the avalanche current to bias the emitter-base junction, or, in other words, to charge the emitter-base junction capacitance, as was described in [5]. Based on these observations, a first set of design guidelines can be defined to reduce the overshoot: increasing the P-well resistance (for example by pushing the base contact away from the emitter or adding an external resistance) and reducing the emitter-base junction capacitance (for example by designing a smaller emitter).…”

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

“…SCRs are ideal ESD protection devices with low on resistance and low capacitance [15][16] [17]. However, their usage is constrained to below 1.2V circuit applications for latch up concerns, unless special designs are in place to resolve this problem, such as placing diode(s) in series with the SCR.…”