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IntroductionBody contacted (BC) core logic/high speed (HS) and Input/Output (I/0) SOI PMOSFETs from 65nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI leads to worst case degradation for the I/0 and HS SOI p-channel MOSFETs. I/0 PMOS devices stressed under HCI conditions at room temperature show NBTI-like behavior at higher stress voltages and combined HCI-NBTI behavior at lower stress voltages. HS PMOS devices stressed under HCI conditions show a combined HCI and NBTI degradation behavior across the entire stress bias range. Both HS and I/0 devices degrade more when HCI stressed with FB at high stress voltages; however the degradation becomes comparable to BC devices at lower stress voltages.Experimental Details BC and FB PD-SOI PMOSFETs were studied in this work based on high perfomance 65nm SOI CMOS technology [1]. The degradation under bias stress was studied for HS devices (Vdd=1.OV, Tox=1.05 nm) with W/L=3/0.06 and for I/0 devices (Vdd=1.5V, Tox=2.35 nm) with W/L=3/0.12. HS devices were subjected to a range of NBTI stress bias and temperature values. Additionally, both types of devices were subjected for a period of time to HCI stress at Vg=Vd, known to lead to worst case degradation for deep submicron PMOSFETs [2]. The stress was briefly interrupted to measure the device characteristics in both forward (FWD) and reverse (REV) mode (drain and source interchanged during measurement) to help probe the degradation mechanism.Results and Discussion Fig. 1 shows the shift of saturation threshold voltage (AVtSat) vs. temperature under different NBTI stress bias values for HS PMOS devices. It is shown in this figure that BC devices degrade more than FB devices [3] for high stress bias and temperature values. This is due to the fact that during stress, negative charge is being collected in the floating body which effectively lowers the oxide field thereby reducing NBTI. That the electric field is lowered in this case is supported by the fact that the (tunneling) gate current is lower in the FB device (Fig. 2). Carrier separation measurements show that the main component of the gate current during stress is holes, which are injected from the Si substrate valence band into the oxide, as shown in Fig. 3. Fig. 4 shows the NBTI degradation behavior for I/0 devices where again the BC devices degrade more than FB devices, also due to the lowered oxide field in the FB devices, as demonstrated by the lower gate (tunneling) current, Fig. 5. Fig. 6 shows the AVtSat vs. stress time for both BC and FB I/0 PMOS devices under Vg=Vd=-2.7V HCI stress at room temperature. It is shown in this figure that for both devices, the FWD and REV mode measurements are exactly on top of each other, demonstrating symmetric degradation along the channel. This symmetric shift in VtSat reveals NBTI degradation dominance under the present HCI stress condition. Fig. 6 also shows pure NBTI degradation at room temperature at Vg=-2.7V and ...

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