Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

We report the data and a model showing that the energy loss experienced by the carriers flowing through breakdown spots is the primary cause of progressive breakdown spot growth. The experiments are performed in gate dielectrics of metal-oxide-semiconductor (MOS) devices subjected to accelerated high electric field constant voltage stress under inversion conditions. The model is analytical and contains few free parameters of clear physical meaning. This is compared to a large set of data on breakdown transients at various oxide thicknesses, stress voltages, and temperatures, both in cases of n-channel and p-channel transistors and polycrystalline Si/oxynitride/Si and metal gate/high k dielectric/Si gate stacks. The basic idea is that the breakdown transient is due to the growth of one or more filaments in the dielectric promoted by electromigration driven by the energy lost by the electrons traveling through the breakdown spots. Both cases of polycrystalline Si/oxynitride/Si and metal gate/high-k dielectric/Si MOS structures are investigated. The best fit values of the model to the data, reported and discussed in the paper, consistently describe a large set of data. The case of simultaneous growth of multiple progressive breakdown spots in the same device is also discussed in detail.

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