2004 IEEE International Reliability Physics Symposium. Proceedings
DOI: 10.1109/relphy.2004.1315308
|View full text |Cite
|
Sign up to set email alerts
|

Impact of stress induced leakage current on power-consumption in ultra-thin gate oxides

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

1
4
0

Publication Types

Select...
4
2

Relationship

0
6

Authors

Journals

citations
Cited by 6 publications
(5 citation statements)
references
References 8 publications
1
4
0
Order By: Relevance
“…And the slow growth of the stress induced leakage currents (SILC) also can be seen more clearly in this figure. The solid curves fitted to the SILC-t stress curves by LSM before t I/II roughly show t 0.3 -dependence at all V g monitor conditions approximately as reported before [47][48][49]. Fig.…”
Section: -4-1 Extractions Of Currents Through Pbd Spotssupporting
confidence: 78%
“…And the slow growth of the stress induced leakage currents (SILC) also can be seen more clearly in this figure. The solid curves fitted to the SILC-t stress curves by LSM before t I/II roughly show t 0.3 -dependence at all V g monitor conditions approximately as reported before [47][48][49]. Fig.…”
Section: -4-1 Extractions Of Currents Through Pbd Spotssupporting
confidence: 78%
“…21,22) Figure 5 shows the V g dependence of the defect generation efficiency, , for poly-Si channel FETs and Si(100) channel FETs. The experimental data for Si(100) reported in the literature 20,23) are also plotted.…”
Section: Comparison Of Defect Generation and Breakdownmentioning
confidence: 99%
“…SILC corresponds to defect generation in the gate oxide and can be described as ÁJ=J 0 ¼ ðQ inj Þ , where is the defect generation efficiency and is the power law exponent. 21,22) Figure 5 shows the V g dependence of the defect generation efficiency, , for poly-Si channel FETs and Si(100) channel FETs. The experimental data for Si(100) reported in the literature 20,23) are also plotted.…”
Section: Comparison Of Defect Generation and Breakdownmentioning
confidence: 99%
“…For digital CMOS circuitry, the soft breakdown phenomenon of gate oxide may cause slowdown of the circuit and increase of standby current, but usually not catastrophic failures of the transistor [21]- [23]. However, for the 3D-OTP memories, soft breakdown can be a problem for the reliable operation of the chip.…”
Section: Antifuse Breakdown Characteristicsmentioning
confidence: 99%