Evaluation of&amp;lt;tex&amp;gt;$hboxSiO_2$&amp;lt;/tex&amp;gt;Antifuse in a 3D-OTP Memory

Li, Feng; Yang, Xiaoyu; Meeks, A.T.; Shearer, J.; Le, Khoa

doi:10.1109/tdmr.2004.837118

Cited by 26 publications

(10 citation statements)

References 22 publications

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“…Our 10-layer NW 3D electronic structure consists of the highest number of functional device layers that have been vertically stacked and reported with any single-crystalline channel material to date. ,− Recent studies using a similar transfer printing of nanomaterials has produced up to three layers with electrical measurements, a factor of 3 less than in this work. In planar Si technology, it has been difficult to achieve true 3D integrated structures, due in part to materials-related challenges associated with high-temperature processing needed to produce single-crystalline silicon.…”

mentioning

confidence: 91%

“…Our 10-layer NW 3D electronic structure consists of the highest number of functional device layers that have been vertically stacked and reported with any single-crystalline channel material to date. 16,[25][26][27][28][29] Recent studies using a similar transfer printing of nanomaterials has produced up to three layers with electrical measurements, 16 a factor of 3 less than in this work. In planar Si technology, it has been difficult to achieve true 3D integrated structures, due in part to materialsrelated challenges associated with high-temperature processing needed to produce single-crystalline silicon.…”

mentioning

confidence: 99%

“…In planar Si technology, it has been difficult to achieve true 3D integrated structures, due in part to materialsrelated challenges associated with high-temperature processing needed to produce single-crystalline silicon. This challenge has been circumvented through wafer-to-layer bonding [25][26][27] and incorporation of poly-Si as the active channel material, 28,29 although both approaches have limitations. Our approach represents a unique opportunity for exploring highperformance 3D integrated circuitry owing to fact that higher temperature materials growth, which enables single-crystalline functional NWs, is independent of the their low processing assembly and fabrication steps used to complete each active electronic layer.…”

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confidence: 99%

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Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

et al. 2007

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We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW fieldeffect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.Over the past several years, semiconductor NWs 1,2 and carbon nanotubes 3 have been actively explored as the potential materials for future electronic components. These chemically derived single-crystalline nanostructures present unique advantages over conventional semiconductors, as they enable integration of high-performance device elements onto virtually any substrate 4-6 with scaled on-currents and switching speeds higher than state-of-the-art planar Si structures. 7,8 These unique electrical properties and the intrinsically miniaturized dimensions of NW and carbon nanotube building blocks may facilitate the continuation of Moore's law and the evolutionary quest for ever faster and smaller electronics well into the future. More uniquely, the capability of assembling high-performance NW building blocks with diverse functional properties could enable novel circuit concepts such as 3D integrated electronics, 9 where 3D structure arises from sequential assembly 10-12 of NWs into vertically stacked device layers.Indeed, there has been considerable interest in multilayer electronics, as they offer a more efficient interconnection and processing of digital information. [13][14][15] However, materials-and fabrication-related challenges have presented major obstacles in achieving truly 3D integrated circuits based on the conventional Si CMOS technology, and the need for a new technology remains critical. Here, we report the monolithic integration of individual and parallel arrays of crystalline NWs as multifunctional and multilayer circuits...

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confidence: 91%

“…Our 10-layer NW 3D electronic structure consists of the highest number of functional device layers that have been vertically stacked and reported with any single-crystalline channel material to date. 16,[25][26][27][28][29] Recent studies using a similar transfer printing of nanomaterials has produced up to three layers with electrical measurements, 16 a factor of 3 less than in this work. In planar Si technology, it has been difficult to achieve true 3D integrated structures, due in part to materialsrelated challenges associated with high-temperature processing needed to produce single-crystalline silicon.…”

mentioning

confidence: 99%

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confidence: 99%

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Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

et al. 2007

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“…Programmable Read-Only Memory (PROM) is a kind of non-volatile memories. It has been widely applied in space fields where superior reliability is required, such as satellite communication and spacecraft electronics [1,2,3]. For space application, PROMs should be hardened against natural radiation in the space.…”

Section: Introductionmentioning

confidence: 99%

A radiation-hardened programmable read only memory for space applications

Xie

Zhang

et al. 2018

IEICE Electron. Express

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A radiation-hardened 64-Kb Programmable Read Only Memory (PROM) fabricated by 0.18 um commercial technology is proposed. The Radiation-Harden-By-Design (RHBD) technique is applied in the design of the PROM. At the cell level, memory cells consisting of two high reliable antifuse elements are used. At the circuit level, robust sense amplifiers are designed with Dual Interlocked Cell (DICE) latches added to the radiation sensitive nodes. Furthermore, the enclosed NMOS and guard rings are applied at the layout level. As the measurement showed, the PROM could operate at the temperature between −55 and +125°C with 55 ns maximum address access time. The TID (Total Ionizing Dose) test showed that irradiation dose to 5M rad(Si) negligibly impacted standby current and access time. In the heavy ion test, no SEU (Single Event Upset) and no SEL (Single Event Latch-up) were observed up to LET (Linear Energy Transfer) of 64.4 Mev·cm 2 /mg.

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“…A 3D optical coupler design [4], 3D RISC processor-cache architecture [5] [6], 3D DRAM architecture [7] were later proposed among other 3D related publications. In 2004, Samsung announced its double stack S3 technology [8] for SRAM stacking (for NAND Flash in 2006 [9]); 3D-OTP memory from Matrix was also demonstrated [10]. Later MITLL has been able to provide 3D sal fabrication services [11] to research institutes involved in the DARPA 3D IC project [12] [13].…”

Section: Introductionmentioning

confidence: 99%

3D technology based circuit and architecture design

2009

2009 International Conference on Communications, Circuits and Systems

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Package stacking, die stacking, wafer stacking, and device stacking are the four different types of three dimensional (3D) technology. Except for package stacking, the other three stacking techniques require special considerations when designing circuits and systems. In this paper, different stacking techniques will first be reviewed, followed by an introduction to the possible applications for 3D circuits and systems, including sensor systems, processor-memory systems, Network-on-Chip designs, and Field-Programmable Gate Arrays. The paper will also provide key design considerations in 3D circuits and systems, and use a sensor system as an example to summarize 3D design issues discussed.

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Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

Cited by 26 publications

References 22 publications

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

A radiation-hardened programmable read only memory for space applications

3D technology based circuit and architecture design

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