Improving and optimizing reliability in future technologies with high-&amp;#x03BA; dielectrics

Linder, B.; Cartier, E.; Krishnan, Siddarth; Wu, E.

doi:10.1109/vldi-dat.2013.6533828

Cited by 6 publications

(2 citation statements)

References 3 publications

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“…2. This type of circuit timing error has been discussed by others as it is observable via conventional RO type measurements [12], [16], [17]. Additionally, many circuit design studies have presented possible design solutions to address this type of timing error [26]- [28].…”

Section: Eye Diagram and Jittermentioning

confidence: 99%

PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic

Jiao

Vaz

et al. 2014

IEEE Trans. Electron Devices

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Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.Index Terms-Jitter, positive bias temperature instability (PBTI), pseudorandom bit sequence (PRBS).

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Section: Eye Diagram and Jittermentioning

confidence: 99%

PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic

Jiao

Vaz

et al. 2014

IEEE Trans. Electron Devices

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show abstract

“…Using the observed voltage and thickness dependence, Fig. 1 shows the voltage reduction requirement for interfacial layer (IL) scaling [4]. The 2013 ITRS roadmap anticipates sufficient voltage reduction to contain the expected impact on nFet T inv scaling, but NBTI will limit pFet scaling unless new materials such SiGe channel devices are adopted [5].…”

Section: Voltage and Tinv Scalingmentioning

confidence: 99%