Latchup in CMOS technology

Hargrove, M.; Voldman, Steven H.; Gauthier, R.; Brown, Jeffrey S.; Duncan, K.; Craig, W.

doi:10.1109/relphy.1998.670561

Cited by 41 publications

(7 citation statements)

References 20 publications

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“…The substrate/ well pickups in internal circuits can decrease the voltage across the emitter/ base junctions of the parasitic BJTs to efficiently improve latchup immunity. However, the wider double guard rings in I/O cells and more pickups in the internal circuits often occupy more layout area in the bulk CMOS ICs [3][4][5][6][7][8]. In 0.13um and below technologies, with mixed signal design, I/O circuit powered by different power supplies is integrated into a common design.…”

Section: Conventional I/o Latch-up: V Dd -To-v Ssmentioning

confidence: 99%

A study of latch-up mechanisms for adjacent pins on multiple power supply circuits

Liang

Guo

et al. 2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Traditional latch-up (V DD -to-V SS ) in CMOS IC's is formed by the parasitic p-n-p-n structure between V DD and V SS . In modern technologies, although the guard rings and substrate/ well pickups could efficiently overcome the latch-up failure in CMOS ICs, the latch-up failure phenomenon is still existed in many special application circuits. With mixed signal design requirements, there are more than 2 kinds of devices that are deployed in one chip to implement the design with higher voltage system on the advanced technologies with lower voltage application in the mixed-voltage process. Therefore, these comprehensive process and design approaches could provide more flexibility for the chips to be connected with older system [1][2]. A latch-up phenomenon is reported here that the latch-up current path occurs between adjacent power pins of 65nm process, IO circuit is powered by different power supplies. In this product, IO circuitry is with 3.3V and core circuitry is with 1.2V power supply. Because there is no V DD -to-V DD latch-up rule, the 3.3V n-well to 1.2V n-well space was < 10 um (note: without any guard rings in between). Latch-up immunity of I/O pins resulted from a higher substrate potential required on the base-emitter junction forward bias of LQpnp. Conventional I/O Latch-Up: V DD -to-V SSLatch-Up is a major and inherent problem in CMOS caused by an internal positive feedback mechanism that gives rise to temporary or permanent loss of circuit function. In CMOS integrated circuits, traditional latchup is formed by the parasitic SCR (Silicon-Controlled-Rectifier) path between V DD and V SS . This parasitic path is inherent in the bulk CMOS ICs. When the SCR path is triggered on to conduct a huge current from V DD to V SS , the chip is often burned out. The equivalent circuit of the SCR path is shown in Fig. 1. (a); and the cross-sectional view of this path in a p-substrate bulk CMOS technology is illustrated in Fig. 1. (b). Necessary conditions for latch-up are that the emitter-base junction of both parasitic bipolar transistors must be forward biased. a) βn*βp > 1, b) V DD > V H , and c) There is a minimum latch-up trigger time for which the stimulus must be present in order for the circuit to be latched up. I-V characteristic of p-n-p-n is shown in Fig. 2. (a) (b) Fig.1. (a) The equivalent circuit, including well and substrate resistance, and (b) The cross-sectional view, of the traditional latch-up path in a p-substrate bulk CMOS technology.Fig.2 I-V characteristic of p-n-p-n P-SubN-Well P-Well P+ P+ N+ SCR Path VDD VSS VQ pnp LQ npn N+ N+ P+ Rwell RSub P-Sub N-Well P-Well P+ P+ N+ SCR Path VDD VSS VQ pnp LQ npn N+ N+ P+ Rwell RSub V H : holding voltage I H : holding current V trig : triggering voltage V H : holding voltage I H : holding current V trig : triggering voltage VSS VDD Rwell RSub LQ pnp VQ npn + + --V EB V BE VSS VDD Rwell RSub LQ pnp VQ npn + + --V EB V BE 78 978-1-4799-0480-8/13/$31.00 c 2013 IEEE

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Section: Conventional I/o Latch-up: V Dd -To-v Ssmentioning

confidence: 99%

A study of latch-up mechanisms for adjacent pins on multiple power supply circuits

Liang

Guo

et al. 2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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“…The latchup issue [18], [19] should be considered when the HVPSCR is used for ESD protection. When ICs are in normal circuit operating conditions, the HVPSCR device could be accidentally triggered on by noise pulse [20].…”

Section: A Device Structure and Turn-on Mechanism Of The Hvpscrmentioning

confidence: 99%

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

Ker

Chang

2007

IEEE Trans. Device Mater. Relib.

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A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-linepulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5-µm high-voltage complementary MOS process. Such ESDenhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 µm, the machine-model ESD levels of the HVPSCR are as high as 1100, 1300, and 1900 V, respectively. Index Terms-Electrostatic discharge (ESD), high-voltage p-type silicon-controlled rectifier (HVPSCR), human body model (HBM), machine model (MM), secondary breakdown current (It2), vacuum fluorescent display (VFD).

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“…The STI technology effectively reduces the current gain of the parasitic lateral bipolar transistor to prevent SEL [5]. The retrograde wells can reduce well resistance and shunt the vertical parasitic bipolar transistor [9].…”

Section: A Sel Testmentioning

confidence: 99%