Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

Abstract

We compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout. The devices are evaluated using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current. We also report that SCR turn-on time is highly dependent on the amplitude of the applied pulse.

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

“…This indicates dependence of the turn-on time on pulse amplitude. The same phenomenon has been observed by Di Sarro et al [20]. They attributed this to the bipolar base-emitter capacitances being charged by a finite current.…”

“…A simple SCR structure might not be efficient for CDM protection. It has been reported that failure current of CDM stress tests for SCR protection is significantly lower than that for ggNMOS structures [20].…”

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32nm

“…1. To avoid any damage, classically, ESD protections are embedded in the whole integrated circuit (IC), and local protections [1][2][3][4][5] are added in signal I/O. Due to ESD control improvement in automated systems, a reduction of Human Body Model (HBM) target from 2 kV in CMOS 45 nm to 1 kV in CMOS 32 nm for digital applications can be observed in the ESD community [6].…”

Complementation SCR for RF IC ESD protection

“…In the whole chip SCR ESD protection scheme, the complementation style SCR (CSCR) is an excellent choice which can achieve a balance among area consumed, ESD robustness and low trigger voltage [4,5]. Various novel layouts of CSCR are designed and figures of merit (FOM) are compared with the traditional local ESD protection in this Letter.…”

“…Turn-on time is defined as the time when current reaches 90% of the saturation current (dashed lines in Fig. 3b) under TLP pulse rise time 0.2 ns and width 100 ns [5].…”