Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

Abstract

SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.

A compact SCR model using advanced BJT models and standard SPICE elements

“…Meanwhile, developing new models based only on existing SPICE models is efficient and highly flexible [4,5]. Using advanced MOSFET and BJT models, these aforementioned works have successfully modeled MOS and modified SCRs respectively.…”

“…As shown in Figure 1(a), this paper proposes an impedance transformation model by adding two VCRs, i.e., R D and R dio , into the SCR's equivalent circuit. Their mathematic expressions are linear piecewise functions described in (5) and (6), When V Rn is high enough, the SCR changes to low impedance state eventually. Therefore, the impedance variation of SCR is modeled.…”

A scalable SCR compact model for ESD circuit simulation

“…To extract the self-heating model parameters, current and power (I, P) are obtained from TLP measurements and a nonlinear least squares best fit is performed on (7). Power is calculated using the relation P = (V anode -V H ) · I, which corresponds to an assumption that heat is generated in the resistive region of the SCR following snapback.…”

“…[2] - [4]. However, there are only limited reports of ESD-SCR compact models [5] - [7] and these models are not fully scalable. While the model presented in this work has several commonalities with that presented in [8], there are some key differences; this model captures self-heating and the effect of layout parameters such as anode to cathode spacing and well tap spacing.…”

A physics-based compact model for SCR devices used in ESD protection circuits

“…Recent works have presented CDM-relevant compact models for SCR-based CMOS protection devices [2]- [6]; however, [2]- [4] are the most applicable to modern CMOS SCRs, as [5]- [6] focus on low voltage triggered SCRs, which turn on more slowly than more recent SCR designs. This paper Figure 1: Representative cross-section of an SCR in a low voltage CMOS process, including the P+ guard ring.…”