On the differences between 3D filamentation and failure of N &amp;#x00026; P type drain extended MOS devices under ESD condition

Shrivastava, Mayank; Bychikhin, S.; Pogány, D.; Schneider, Jens; Baghini, Maryam Shojaei; Gossner, Harald; Gornik, E.; Rao, V. Ramgopal

doi:10.1109/irps.2010.5488785

Cited by 7 publications

(5 citation statements)

References 8 publications

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“…An ideal current source (defined pulse shape) is used as the stress stimulus during electrothermal TCAD simulations with proper electrical and thermal contacts. The 3-D TCAD simulation approach is borrowed from our previous works [2], [4]. Various physical models are included to capture high field and high current effects, such as avalanche action, carrier recombination (Shockley-Read-Hall (SRH) and auger), and electric field-dependent mobility degradation models.…”

Section: Understanding the Root Cause Of Failurementioning

confidence: 99%

“…High-voltage laterally double diffused MOS (LDMOS)-/ drain-extended nMOS (DeNMOS) devices cannot be used at the high-voltage pins as their failure current per unit area is small, resulting in unacceptably large cell size and capacitance [1]. The low failure current levels in high-voltage LDMOS/DeNMOS devices are attributed to space charge modulation (SCM)-induced filament formation at the onset voltage snapback [1]- [4]. Though previous works in [5], [6] tried to improve the LDMOS/DeNMOS ESD robustness, device survival beyond snap-back cannot be guaranteed.…”

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confidence: 99%

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System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

Kranthi

Sarro

Sankaralingam

et al. 2021

IEEE Trans. Electron Devices

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A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure. Index Terms-Current filaments, drain-extended nMOS [laterally double diffused MOS (LDMOS)], electrostatic discharge (ESD), International Electrotechnical Commission (IEC), system-level ESD. I. INTRODUCTIONT HE electrostatic discharge (ESD) protection design is particularly challenging in automotive applications because product requirements often dictate qualification for a variety of stress models in addition to human body model (HBM) and charge device model (CDM). For example, the communication Manuscript

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Section: Understanding the Root Cause Of Failurementioning

confidence: 99%

mentioning

confidence: 99%

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

Kranthi

Sarro

Sankaralingam

et al. 2021

IEEE Trans. Electron Devices

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“…Under a positive voltage ESD stress at the drain, with the source grounded, breakdown takes place in the junction HVNW/Pwell and the parasitic NPN transistor turns on and discharges the ESD current. However, for conventional LDNMOS, it is not easy to get good ESD robustness [3], [4]. Especially, after avalanche breakdown in the latter case, the parasitic NPN transistor conducts and a large electron current is injected from the source (emitter) to the drain (collector), which may result in a strong snapback.…”

Section: Introductionmentioning

confidence: 99%

“…A high V hold can be achieved by decreasing current gain β of the parasitic NPN transistor [8], stacking the low-holding-voltage devices [2] or applying a non-snapback LDPMOS [4], [10] whose parasitic β is much lower than LDNMOS, but it may be damaged just after snapback as mentioned above or need more design work. Fig.…”

Section: Introductionmentioning

confidence: 99%

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Fan

Jiang

Zhang

2013

IEEE Trans. Device Mater. Relib.

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High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.Index Terms-ESD, high holding voltage, LDNMOS.

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“…However, we found that devices like drain extended MOS [9] or in general devices which suffer from heavy charge modulation at early currents, cannot be modeled using 2D device simulations. As discussed in [10], since the modeling for the ESD behavior of various devices [11]- [13] is normally based on 2D simulations, it lacks the physical insight required to predict the 3D filamentation and failure. Moreover we also found that 2D simulations for ggNMOS or SCR like structures underestimate the It2 value [14].…”

Section: Introductionmentioning

confidence: 99%

3D TCAD based approach for the evaluation of nanoscale devices during ESD failure

Shrivastava

Gossner

Baghini

et al. 2010

2010 International SoC Design Conference

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On the differences between 3D filamentation and failure of N & P type drain extended MOS devices under ESD condition

Cited by 7 publications

References 8 publications

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

3D TCAD based approach for the evaluation of nanoscale devices during ESD failure

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