Analysis of the design space available for high-kgate dielectrics in nanoscale MOSFETs

Frank, D.J.; Wong, Hang

doi:10.1006/spmi.2000.0952

Cited by 14 publications

(8 citation statements)

References 4 publications

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“…The scale length theory of Section II-A shows that the physical thickness of the high-insulator becomes important as increases, increasing the scale length and the drain potential penetration under the gate [19], [33]. This is illustrated in Fig.…”

Section: B Tunneling Limitsmentioning

confidence: 94%

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Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Section: B Tunneling Limitsmentioning

confidence: 94%

“…(c) 2-D numeric simulation for a high-k gate insulator (k = 78, 30 nm thick) with extreme ground-plane-likedoping profiles and shallow source and drain. From[33].…”

mentioning

confidence: 99%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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“…When the high-permittivity region is confined to the channel area alone, not extending over the heavily doped source and drain, this path is cut off. As noted by Frank [54], this does not change the scale length, since the same equations are solved in the channel cross section; rather, it introduces an extra attenuation in the form of a pre-factor into the equation describing the drain-induced potential along the channel. This pre-factor attenuation is a rapidly increasing function of the permittivity of the dielectric; if it is large enough, it may in itself be sufficient to give the…”

Section: The Ultimate (Silicon) Fetmentioning

confidence: 99%

Silicon CMOS devices beyond scaling

Nowak²,

et al. 2006

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To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/lm for the 250-nm node to hundreds of nA/lm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit. Gate length (nm) ERROR: See p. 361A.

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“…Leakage current reduction from 10 3 ϫ to 10 6 ϫ, in comparison with SiO 2 of the same electrical thickness, is generally achieved experimentally for high-k gate dielectrics [21]. The benefits of using a very-highdielectric-constant material to simply replace SiO 2 for the same electrical thickness are limited because of the presence of two-dimensional electric fringing fields from the drain through the physically thicker gate dielectric [10,22]. The drain fringing field lowers the source-to-channel potential barrier and lowers the threshold voltage in a way similar to the well-known drain-induced barrier lowering (DIBL), in which the drain field modulates the source-tochannel potential barrier via coupling through the silicon substrate.…”

Section: High-k Gate Dielectricmentioning

confidence: 98%

Beyond the conventional transistor

2002

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This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials.Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

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Analysis of the design space available for high-kgate dielectrics in nanoscale MOSFETs

Cited by 14 publications

References 4 publications

Device scaling limits of Si MOSFETs and their application dependencies

Device scaling limits of Si MOSFETs and their application dependencies

Silicon CMOS devices beyond scaling

Beyond the conventional transistor

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