Analysis of the electrical characteristics and structure of Cu-Filled TSV with thermal shock test

Jeong, Il Ho; Roh, Myong Hoon; Jung, Flora; Song, Wenjing; Mayer, Michael; Jung, Jae Pil

doi:10.1007/s13391-013-3260-6

Cited by 14 publications

(2 citation statements)

References 5 publications

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“…TSV three-dimensional integrated devices with internal defects will gradually be failed by thermal mechanical stress, electrical stress, and other stresses, which will greatly affect TSV three-dimensional device reliability [3][4]. Ranganathan et al [5] studied the influence of a fan-shaped interface generated by the Bosch etching process on TSV thermal stress.…”

Section: Introductionmentioning

confidence: 99%

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Yuan¹,

Zhang²,

Xia³

et al. 2019

IJPE

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TSV technology can achieve heterogeneous integration by stacking different technologies and functions of logic chip, memory, MEMS, etc., as a system. There are many significant advantages for heterogeneous integration in terms of cost, performance, and time to market. TSV technology has the potential to improve 3D packaging. As the important physical connection and electrical connection between the chips, TSV's reliability is undoubtedly the key to determine the reliability of TSV three-dimensional integrated devices. As a new interconnect technology, TSV technology faces many process difficulties and challenges. Its reliability has not been fully studied and guaranteed. The process optimization and reliability improvement of TSV have become a hot topic in recent years. Recognition process defects and analysis of the failure mechanism play important roles in the optimization and improvement of design, production, and use of TSV three-dimensional integrated devices. In this paper, the square TSV and circular TSV with different ratios were researched by microphysical analysis and data analysis. The analysis results revealed the key technological factors and physical mechanism of formation of the TSV defects, which can support TSV device development, production, and reliable application.

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Section: Introductionmentioning

confidence: 99%

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Yuan¹,

Zhang²,

Xia³

et al. 2019

IJPE

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“…During the thermal cycling, thermal stresses will develop in the TSV interconnect structure and in surrounding Si substrate due to the mismatch in coefficient of thermal expansion (CTE) between TSV material, dielectric, and Si substrate. This will cause reliability issues such as via extrusion, cracking, voids, delamination, and mobility degradation of device performance [7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Characterization of local strain/stress in copper through-silicon via structures using synchrotron x-ray microdiffraction, electron backscattered diffraction and nonlinear thermomechanical model

Song

Mundboth

Szpunar

et al. 2015

J. Micromech. Microeng.

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In this study, the thermomechanical characteristics of copper through-silicon via (Cu TSV) structures were studied using synchrotron x-ray microdiffraction, electron backscattered diffraction (EBSD), and nonlinear numerical modeling. The strain and stress distribution in the Si substrate was measured by synchrotron x-ray microdiffraction from the tops of the TSV structures. The strain distribution map in a Cu via was determined from EBSD data by the kernel average misorientation (KAM) method and microstructural characteristics of the Cu via were investigated. The results offered direct evaluation of the local strain and stress induced in the Cu via and its surrounding silicon substrate. A finite element model including nonlinear plastic deformation was built for predicting thermomechanical behaviors of Cu TSV structures. The results show that the stress distribution obtained by finite element modeling is in relatively good agreement with the measurements of synchrotron x-ray microdiffraction and EBSD.

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Effect of SiC nanoparticles on SAC305-TSV reliability under thermal load

Wang

et al. 2022

J Mater Sci

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Analysis of the electrical characteristics and structure of Cu-Filled TSV with thermal shock test

Cited by 14 publications

References 5 publications

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Characterization of local strain/stress in copper through-silicon via structures using synchrotron x-ray microdiffraction, electron backscattered diffraction and nonlinear thermomechanical model

Effect of SiC nanoparticles on SAC305-TSV reliability under thermal load

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