Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

Pavanello, Marcelo Antonio; Martino, João Antônio; Simoen, Eddy; Claeys, Cor

doi:10.1016/j.sse.2007.07.016

Cited by 4 publications

(4 citation statements)

References 25 publications

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“…The mobility improvement observed in strained-Si channel MOSFETs has been explained by means of the reduction of the carrier conductivity-effective mass and the intervalley scattering rates. In the literature successful improvements by the use of strain in planar silicon-on-insulator (SOI) devices with ultrathin body can be found, not only for the carrier mobility [9][10][11] but also for the low frequency noise [12], the analog performance [13] and the linearity [14].…”

Section: Introductionmentioning

confidence: 99%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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“…Their exploitation will be demonstrated on selected study cases of various advanced devices in wide temperature and frequency ranges, performed in our laboratory over the last years . In order to be complete, important works of other groups in the domain of device assessment for analog/RF applications are also listed [3,10,13,23,[79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95].…”

Section: Introductionmentioning

confidence: 99%

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

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This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the "extrinsic" parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of "intrinsic" versus "extrinsic" parameters.

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“…In the latter case, epitaxially grown Si x Ge 1-x relaxed buffer layers are formed with the desired lattice parameter where on top a monocrystalline strained silicon layer is obtained (4). In the literature successful improvements by the use of strain in planar Silicon-On-Insulator (SOI) devices with ultrathin body can be found, not only for the carrier mobility (5) but also for the low frequency noise (6), the analog performance(7) and the linearity (8). Thus, the use of strained material in FinFETs is of interest because it can contribute to the electron mobility increase in narrow devices.…”

Section: Introductionmentioning

confidence: 99%

Influence of Fin Width and Channel Length on the Performance of Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

et al. 2009

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In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.

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Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

Cited by 4 publications

References 25 publications

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Influence of Fin Width and Channel Length on the Performance of Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

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