The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing the burden, to Department of Defense. Washington Headquarters Services. Directorate for Information Under the leadership of Dr. Rogacki and Dr. Albertani there was significant progress made in delivering a hardware-in-the-loop rapid prototyping capability at the UF-REEF. Embedded systems are designed to control complex plants such as land vehicles, satellites, spacecrafts, unmanned aerial vehicles (UAVs), aircrafts, weapon systems, marine vehicles, and jet engines. They generally require a high level of complexity within the embedded system to manage the complexity of the plant under control. Hardware-in-the-Loop (HIL) simulation is a technique that is used increasingly in the development and test of complex real-time embedded systems.The purpose of HIL simulation is to provide an effective platform for developing and testing real-time embedded systems. HIL simulation provides an effective platform by adding the complexity of the plant under control to the test platform. The complexity of the plant under control is included in test and development by adding a mathematical representation of all related dynamic systems. These mathematical representations are referred to as the "plant simulation.'" The UF-REEF has established a HIL simulation capability for MAV's that will lead to a rapid prototyping capability.The Task 1 research plan included testing the visual based control system running on the cluster PCs in the REEF Visualization Lab by flying a relatively stable off the shelf slow flier (similar to MAV flight regime) in the small REEF wind tunnel and later in the large wind tunnel. The general layout of the test bed is illustrated in Fig. 2.