Analysis on Self-Heating Effect in 7 nm Node Bulk FinFET Device

Abstract

Abstract-The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From selfheating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Selfheating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.

Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

“…In order to reduce short channel effects (SCEs) known as secondary effects, the structures of threedimensional transistor have been developed and used. The FinFET is the most used commercially available three-dimensional MOSFET [1][2][3][4]. The existing three-dimensional structure mainly used an inversion-type MOSFET using a junction-based structure with different doping type and concentration between source/drain and channel, but recently reached the limit of the technology of forming a junction with decreasing channel length to nano unit [5][6][7][8].…”