Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory

Jung, Bo-Sung; Lee, Junghoon

doi:10.14372/iemek.2012.7.4.201

IEMEK Journal of Embedded Systems and Applications

2012

DOI: 10.14372/iemek.2012.7.4.201

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Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory

Bo-Sung Jung¹,

Junghoon Lee²

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An Asymmetry Matrix Transposition Scheme based on NAND Flash Memory

Kim¹,

Park²,

On³

et al. 2015

IEMEK Journal of Embedded Systems and Applications

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: In this paper, we proposed a new matrix transposition scheme, called asymmetry sub-matrix, and conducted the in-depth performance evaluation of the proposed scheme with other prior schemes, including element-major, row-major and sub-matrix schemes in large-scale matrix. In our results, the proposed asymmetry sub-matrix scheme shows the best performance compared to other prior schemes, while sub-matrix scheme shows the second best performance.

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An Asymmetry Matrix Transposition Scheme based on NAND Flash Memory

Kim¹,

Park²,

On³

et al. 2015

IEMEK Journal of Embedded Systems and Applications

View full text Add to dashboard Cite

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PCM Main Memory for Low Power Embedded System

Lee¹

2015

IEMEK Journal of Embedded Systems and Applications

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: Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories -the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

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High Performance PCM&DRAM Hybrid Memory System

Jung¹,

Lee²

2016

IEMEK Journal of Embedded Systems and Applications

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: In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

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Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory

Cited by 3 publications

References 1 publication

An Asymmetry Matrix Transposition Scheme based on NAND Flash Memory

An Asymmetry Matrix Transposition Scheme based on NAND Flash Memory

PCM Main Memory for Low Power Embedded System

High Performance PCM&DRAM Hybrid Memory System

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