Analytic evaluation of shared-memory systems with ILP processors

Sorin, D.T.; Pai, Vijay S.; Adve, Sarita V.; Vemon, M.K.; Wood, David А.

doi:10.1109/isca.1998.694797

Cited by 40 publications

(16 citation statements)

References 30 publications

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“…They also measured the improved MLP by measuring MSHR utilizations. Many other works [30,15] also used the number of occupied MSHRs or stall cycles due to full MSHRs to measure MLP. Zhou and Conte [32] used value prediction techniques to increase MLP by parallelizing loads that were sequentially dependent.…”

Section: Memory-level Parallelismmentioning

confidence: 99%

Elf

Park

Mahlke

2015

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

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Graphics processing units (GPUs) are increasingly utilized as throughput engines in the modern computer systems. GPUs rely on fast context switching between thousands of threads to hide long latency operations, however, they still stall due to the memory operations. To minimize the stalls, memory operations should be overlapped with other operations as much as possible to maximize memory-level parallelism (MLP). In this paper, we propose Earliest Load First (ELF) warp scheduling, which maximizes the MLP by giving higher priority to the warps that have the fewest instructions to the next memory load. ELF utilizes the same warp priority for the fetch scheduling so that both are coordinated. We also show that ELF reveals its full benefits when there are fewer memory conflicts and fetch stalls. Evaluations show that ELF can improve the performance by 4.1% and achieve total improvement of 11.9% when used with other techniques over commonly-used greedy-then-oldest scheduling. CCS Concepts •Computer systems organization → Single instruction, multiple data; •Software and its engineering → Runtime environments;

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Section: Memory-level Parallelismmentioning

confidence: 99%

Elf

Park

Mahlke

2015

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

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“…Processors' structures are so complex that few analytical models can be provided for them. Some research efforts are presented by Noonburg and Shen (1997) using a Markov models to model a pipelined processor, when Sorin et al (1998) used probabilistic techniques to model a Multi-processor composed by superscalar processors.…”

Section: Analytical-based Approachmentioning

confidence: 99%

Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances

Mhadhbi

Litayem

Othman

et al. 2014

Complex System Modelling and Control Through Intelligent Soft Computations

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Due to their flexible architecture, lower-cost and faster processing, Field Programmable Gate Array (FPGA) presents one of the stimulating choices for implementing modern embedded systems. This is due to their intrinsic parallelism, fast processing speed, rising integration scale and lower-cost solution. This kind of platforms can be considered as a futuristic implementation platform. The growing configurable logic capacity of FPGA has enabled designers to incorporate one or more processors in FPGA platform. In contrast to the traditional hard cores, the soft cores processors present an interesting solutions for implementing embedded applications. They give designers the ability to adapt many configurations to their specific application; including memory subsystems, interrupt handling, ISA features, etc. Faced to the various problems related to the selection of an efficient soft-core FPGA embedded processor with appropriate configuration, co-design methodology presents a good deal for embedded designers. The most crucial step in the design of embedded systems is the hardware/software partitioning. This step consists of deciding which component is suitable for hardware implementation and which one is more appropriate for software implementation. This research field is especially active (always on the move) and several approaches are proposed. In this chapter, we will present our contribution on the hardware/software partitioning co-design approach, and discuss their involvement on design acceleration and architecture performances. The first part of this chapter describes the effect of the MicroBlaze Xilinx configuration on the embedded system performance. The second part

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“…Loh described a time-stamping method [17] that processes dynamic instructions one by one instead of simulating cycle by cycle as in cycle-accurate performance models. A form of time-stamping had already been implemented in the DirectRSIM multiprocessor simulator [4,26]. Loh's time-stamping method uses scoreboards to model the impact of certain limited resources (e.g., ALUs).…”

Section: Structural Core Modelsmentioning

confidence: 99%

BADCO: Behavioral Application-Dependent Superscalar Core Models

Velásquez

Michaud

Seznec

2013

Int J Parallel Prog

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International audienceMicroarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approximate microarchitecture models, which trade accuracy for simulation speed, are very useful for research and design space exploration, provided the loss of accuracy remains acceptable. Behavioral superscalar core modeling is a possible way to trade accuracy for simulation speed in situations where the focus of the study is not the core itself. In this approach, a superscalar core is viewed as a black box emitting requests to the uncore at certain times. A behavioral core model can be connected to a detailed uncore model. Behavioral core models are built from detailed simulations. Once the time to build the model is amortized, important simulation speedups can be obtained. We describe and study a new method for defining behavioral models for modern superscalar cores. The proposed Behavioral Application-Dependent Superscalar Core model, BADCO, predicts the execution time of a thread running on a superscalar core with an error less than 10% in most cases. We show that BADCO is qualitatively accurate, being able to predict how performance changes when we change the uncore. The simulation speedups we obtained are typically between one and two orders of magnitude

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Analytic evaluation of shared-memory systems with ILP processors

Cited by 40 publications

References 30 publications

Elf

Elf

Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances

BADCO: Behavioral Application-Dependent Superscalar Core Models

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