Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Lin, Cheng-Wu; Lee, Chung‐Lin; Lin, Jai-Ming; Chang, Soon-Jyh

doi:10.1145/2429384.2429520

Cited by 11 publications

(3 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It takes considerable efforts to compose a complete layout synthesis flow from fundamental devices to detailed routing [38,92,93] . This significant development overhead discourages the research in performance-driven AMS layout synthesis.…”

Section: Open-source Efforts On Comprehensive Layout Synthesis Flowmentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

View full text Add to dashboard Cite

Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

show abstract

Section: Open-source Efforts On Comprehensive Layout Synthesis Flowmentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

View full text Add to dashboard Cite

show abstract

“…[16] mentioned the chirality condition of transistors within a common-centroid structure, such chirality condition cannot achieve the best current matching with the impact of gate misalignment. Other recent works [7,8,9,10,11,12] focus on the optimization of common-centroid capacitor placement, but the capacitors in these works are still not associated with the FinFET technology.…”

Section: Introductionmentioning

confidence: 99%

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

View full text Add to dashboard Cite

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

show abstract

“…Although layout synthesis techniques for ratioed capacitors had been extensively studied, most of the previous works [2,7,8,9,10,11,13,16,17] only emphasized how to generate highly matched common-centroid and/or dispersive placements for ratioed capacitors to minimize the impact from random and systematic mismatch. They failed to consider the routing-induced parasitics which may destroy the resulting matching properties of ratioed capacitors even if the placement is perfectly matched.…”

Section: Introductionmentioning

confidence: 99%

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Hsiao

Lin

2014

Proceedings of the 51st Annual Design Automation Conference

View full text Add to dashboard Cite

Capacitor sizing is a crucial step when designing a chargescaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

show abstract

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Cited by 11 publications

References 23 publications

Challenges and opportunities toward fully automated analog layout design

Challenges and opportunities toward fully automated analog layout design

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Contact Info

Product

Resources

About