Analytical delay computation for arbitrary distributed RLC trees

Abstract

Absfracf-As feature size decreases and circuit size and complexity increases, interconnect plays B dominating role in determining the overall circuit performance, reliability and c0s.t. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominntes the delay due to transistors. In this paper, we present a dosed-form delay calculation approach for distributed RLC interconnect trees that addresses shortcoming with past interconnect models. 1. NTRODUCTION < Integrated circuits (IC) trends toward DSM techndlogy have undoubtedly made the interconnect delay the most dominant factor influencing circuit performance. Furthermore, the use of increasingly hi,gher frequency of operation implies that the inductive effects of interconnects can no longer be ignored, as doing so may result in severely underestimating the delay [ 11 [2]. This is further corroborated by the fact that'.at high operation frequencies, the transition time of the input signals is often comparable, or less +n, the propagating signals' time of flight. Therefore, the interconnect inductance should be considered. Early analysis of ICs modelled interconnects as lumped or distributed RC lines. This naturally led to extensive studied materials as well as delay calculation models being available for VLSI circuit performance analysis and optimisation for those models. One of the widely used delay calculation models for performance-driven synthesis and layout of VLSI routing technology for lumped RC lines is the Elmore delay model. However, its estimation result can be quite pessimistic, as error margins of up to 60% have been reported using this delay model. Moreover, given the non-monotonic nature of present interconnect lines induced by the inductive effects, the Elmore interconnect delay calculation is only applicabfe to RC interconnect trees and not to distributed RLC lines. To address these shortcomings, alternative models based on moment-matching techniques were recently proposed in [3] [ 4 ] [ 5 ] . Although the majority of those modcls have a much faster estimation time than simulation tools such as SPICE, the vast majority of them still remain computationally expensive and can be numerically unstable [6]. In addition, they have been mostly used for lumped RLC interconnect networks which is misrepresentative of the realistic distributed RLC line nature of present VLSI interconnects. More recent works proposed in 171 and [6], den1 with the distributive effects of the IUC line. However, in[7], the authors found a time-domain expression of the line transfer function and proposed a delay calculation that involves Bessel function, which limits the flexibility of their expression for other applications such as interconnect optimisation through repeater insertion. Furthermore, their analyses are based on a distributed RLC line with arbitrary series impedance, therefore misrepresentative of the practical VLSI interconnect model. The analytical delay expression model presented in [6] was derived by...