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In the past, gate delay was the dominant factor in determining circuit performance. However, as feature size becomes smaller and chip area becomes larger in integrated circuits, interconnect delay has become an increasingly important factor in determining circuit performance. In this paper, we present an analytical delay calculation approach for a distributed RLC interconnect line that maintains the effectiveness and the efficiency of past RC interconnect models, but significantly improving their accuracy for deep submicron (DSM) designs.

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Absfracf-As feature size decreases and circuit size and complexity increases, interconnect plays B dominating role in determining the overall circuit performance, reliability and c0s.t. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominntes the delay due to transistors. In this paper, we present a dosed-form delay calculation approach for distributed RLC interconnect trees that addresses shortcoming with past interconnect models. 1. NTRODUCTION < Integrated circuits (IC) trends toward DSM techndlogy have undoubtedly made the interconnect delay the most dominant factor influencing circuit performance. Furthermore, the use of increasingly hi,gher frequency of operation implies that the inductive effects of interconnects can no longer be ignored, as doing so may result in severely underestimating the delay [ 11 [2]. This is further corroborated by the fact that'.at high operation frequencies, the transition time of the input signals is often comparable, or less +n, the propagating signals' time of flight. Therefore, the interconnect inductance should be considered. Early analysis of ICs modelled interconnects as lumped or distributed RC lines. This naturally led to extensive studied materials as well as delay calculation models being available for VLSI circuit performance analysis and optimisation for those models. One of the widely used delay calculation models for performance-driven synthesis and layout of VLSI routing technology for lumped RC lines is the Elmore delay model. However, its estimation result can be quite pessimistic, as error margins of up to 60% have been reported using this delay model. Moreover, given the non-monotonic nature of present interconnect lines induced by the inductive effects, the Elmore interconnect delay calculation is only applicabfe to RC interconnect trees and not to distributed RLC lines. To address these shortcomings, alternative models based on moment-matching techniques were recently proposed in [3] [ 4 ] [ 5 ] . Although the majority of those modcls have a much faster estimation time than simulation tools such as SPICE, the vast majority of them still remain computationally expensive and can be numerically unstable [6]. In addition, they have been mostly used for lumped RLC interconnect networks which is misrepresentative of the realistic distributed RLC line nature of present VLSI interconnects. More recent works proposed in 171 and [6], den1 with the distributive effects of the IUC line. However, in[7], the authors found a time-domain expression of the line transfer function and proposed a delay calculation that involves Bessel function, which limits the flexibility of their expression for other applications such as interconnect optimisation through repeater insertion. Furthermore, their analyses are based on a distributed RLC line with arbitrary series impedance, therefore misrepresentative of the practical VLSI interconnect model. The analytical delay expression model presented in [6] was derived by...

The increase of clock frequency into the GHz all return currents follow DC paths as some are in the form range, coupled with longer length interconnects of small of displacement current through the interconnect cross-section and low dielectric strength, can result in cross-capacitance. For accurate estimation of delay and crosstalk, coupling effects between on-chip interconnects. In this paper, on-chip interconnects are better represented as distributed we propose a four-reflection wave propagation based RLC lines. Therefore, the commonly and generally well analytical model for estimation of crosstalk. An emphasis was made on the distributed nature of the RLC model used, thus accepted Elmore delay calculation has become inapplicable underlining the effect of parasitic coupling inductance and due to the non-monotonic characteristics induced by capacitance on present and future on-chip interconnects.inductances [11] [12].Pillage extended the concept of two-poles one-zero transfer Keywords -Interconect,crossalkdistrbutedRLC function approximation by Horowitz and introduced Keywords Interconnect, crosstalk, distributed RLC.AsmticWvfrEalton( E)orupeRL Asymptotic Waveform Evaluation (AWVE) for lumped RLC networks [13]. His technique is based on explicitly I. INTRODUCTION matching the first '2q-1' moments of the transfer function using Pade approximation as opposed to Elmore who only Crosstalk noise due to capacitive coupling between signal considered the first moment. Such moment matching was wires can result in functional failure or introduce delays later used to predict the time-domain or frequency domain into the circuit. Hence, creating the need for the response of a linear and non-linear network either development of design tools and analysis models for monotonic or non-monotonic over a range of excitation crosstalk noise and delay analysis and estimation for frequencies. Despite it is straightforward in its application efficient circuit design optimisation as well as for post and generally well accepted in the industry due to its layout circuit verification. Although advances have been superior estimation time, AWE suffers from numerical made in the extraction of a detailed RC(L) network for all instability [14] and has been used mostly for lump RLC signal lines, the simulation of an entire RC interconnect interconnect networks. Still in the same class, other tree is computationally expensive. The SPICE simulator algorithms such as Arnoldi, Lanczos and improved Arnoldi remains an excellent tool for small size RC(L) networks as (PRIMA) have been developed. Both Lanczos and PRIMA it provides accurate and efficient estimation results. are numerically stable but only the later keeps passivity. In However, as the number of signal lines exceeds the million [15], the authors proposed an RLC model by approximating figure, in today's integrated circuits (ICs), SPICE the transfer function of the line to a second-order Pade simulation becomes inefficient and time consuming to do approximation of the line. Although th...