The increase of clock frequency into the GHz all return currents follow DC paths as some are in the form range, coupled with longer length interconnects of small of displacement current through the interconnect cross-section and low dielectric strength, can result in cross-capacitance. For accurate estimation of delay and crosstalk, coupling effects between on-chip interconnects. In this paper, on-chip interconnects are better represented as distributed we propose a four-reflection wave propagation based RLC lines. Therefore, the commonly and generally well analytical model for estimation of crosstalk. An emphasis was made on the distributed nature of the RLC model used, thus accepted Elmore delay calculation has become inapplicable underlining the effect of parasitic coupling inductance and due to the non-monotonic characteristics induced by capacitance on present and future on-chip interconnects.inductances [11] [12].Pillage extended the concept of two-poles one-zero transfer Keywords -Interconect,crossalkdistrbutedRLC function approximation by Horowitz and introduced Keywords Interconnect, crosstalk, distributed RLC.AsmticWvfrEalton( E)orupeRL Asymptotic Waveform Evaluation (AWVE) for lumped RLC networks [13]. His technique is based on explicitly I. INTRODUCTION matching the first '2q-1' moments of the transfer function using Pade approximation as opposed to Elmore who only Crosstalk noise due to capacitive coupling between signal considered the first moment. Such moment matching was wires can result in functional failure or introduce delays later used to predict the time-domain or frequency domain into the circuit. Hence, creating the need for the response of a linear and non-linear network either development of design tools and analysis models for monotonic or non-monotonic over a range of excitation crosstalk noise and delay analysis and estimation for frequencies. Despite it is straightforward in its application efficient circuit design optimisation as well as for post and generally well accepted in the industry due to its layout circuit verification. Although advances have been superior estimation time, AWE suffers from numerical made in the extraction of a detailed RC(L) network for all instability [14] and has been used mostly for lump RLC signal lines, the simulation of an entire RC interconnect interconnect networks. Still in the same class, other tree is computationally expensive. The SPICE simulator algorithms such as Arnoldi, Lanczos and improved Arnoldi remains an excellent tool for small size RC(L) networks as (PRIMA) have been developed. Both Lanczos and PRIMA it provides accurate and efficient estimation results. are numerically stable but only the later keeps passivity. In However, as the number of signal lines exceeds the million [15], the authors proposed an RLC model by approximating figure, in today's integrated circuits (ICs), SPICE the transfer function of the line to a second-order Pade simulation becomes inefficient and time consuming to do approximation of the line. Although th...
