Analytical ramp delay model for distributed on-chip RLC interconnects

Abstract

In the past, gate delay was the dominant factor in determining circuit performance. However, as feature size becomes smaller and chip area becomes larger in integrated circuits, interconnect delay has become an increasingly important factor in determining circuit performance. In this paper, we present an analytical delay calculation approach for a distributed RLC interconnect line that maintains the effectiveness and the efficiency of past RC interconnect models, but significantly improving their accuracy for deep submicron (DSM) designs.

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“…For appropriate values of d i and s i , the above recursive equation can be solved numerically using Newton Raphson method by setting [5] as an initial value. In most cases the number of iterations is less than 10.…”

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