Analytical estimation of propagation delay and short-circuit power dissipation in CMOS gates

Nikolaidis, S.; Chatzigeorgiou, Alexander

doi:10.1002/(sici)1097-007x(199907/08)27:4<375::aid-cta64>3.0.co;2-7

Cited by 8 publications

(3 citation statements)

References 16 publications

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“…This approach is similar to that proposed by other authors [10,11], but using a simpler characterization method. The triangular shape is defined by three points: the triangle starting point instant (T b ), the current maximum value and the instant when it takes place (T max ,I max ), and the instant time where the triangle ends (T e ).…”

Section: -Amentioning

confidence: 99%

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Logic-Level Fast Current Simulation for Digital CMOS Circuits

Clavijo

Juan-Chico

Díaz

et al. 2005

Lecture Notes in Computer Science

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Abstract. Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimations when working at higher levels (logic, RT, architectural levels). To solve this problem it is not only necessary to use good current models for switching activity but, also, it is necessary to calculate this switching activity with high accuracy. In this paper we present an alternative to estimate current consumption using logic-level simulation. To do that, we use a simple but accurate enough current model to calculate the current consumption for each signal transition, and a delay model that obtains high accuracy when it is used to measure the switching activity (the Degradation Delay Model -DDM-). In the paper we present the current model for CMOS inverter, the characterization process and the model implementation in the logic simulator HALOTIS that includes the DDM. Results show a high accuracy in the estimation of current curves when compared to HSPICE, and a potentially large improvement over conventional approaches.

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Section: -Amentioning

confidence: 99%

“…Then, power consumed at every node is computed by using charge-based power models. On the other hand, current curves may be generated during logic-level simulation by using current models in a event-driven basis [10,11].…”

Section: Introductionmentioning

confidence: 99%

Logic-Level Fast Current Simulation for Digital CMOS Circuits

Clavijo

Juan-Chico

Díaz

et al. 2005

Lecture Notes in Computer Science

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“…Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market. Although there are several circuit design objectives to be considered during floorplanning, such as area minimization, wirelength optimization [9], delay reduction [10,11], thermal stability [12][13][14], clock tree synthesis [15] or any combination of these objectives [16][17][18], the basic objective of floorplanning is to minimize the area of the VLSI chip.…”

Section: Introductionmentioning

confidence: 99%

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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Efficient output waveform evaluation of a CMOS inverter based on short‐circuit current prediction

Chatzigeorgiou

Nikolaidis

2002

Circuit Theory & Apps

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SUMMARYA novel approach for obtaining the output waveform, the propagation delay and the short-circuit power dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit di erential equation only for the conducting transistor while the e ect of the short-circuit current is considered as an additional charge, which has to be discharged through the conducting transistor causing a shift to the output waveform. The short-circuit current as well as the corresponding discharging current are accurately predicted as functions of the required time shift of the output waveform. A program has been developed that implements the proposed method and the results prove that a signiÿcant speed improvement can be gained with a minor penalty in accuracy.

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Analytical estimation of propagation delay and short-circuit power dissipation in CMOS gates

Cited by 8 publications

References 16 publications

Logic-Level Fast Current Simulation for Digital CMOS Circuits

Logic-Level Fast Current Simulation for Digital CMOS Circuits

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Efficient output waveform evaluation of a CMOS inverter based on short‐circuit current prediction

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