Analytical Model Developed for Precise Stress Estimation of Device Channel Within Advanced Planar MOSFET Architectures

Lee, Chang‐Chun; Huang, Pei‐Chen; Lin, YuanYao

doi:10.1109/ted.2020.2971715

Cited by 4 publications

(2 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When the distance between the TSV origin and Si pMOSFET is fixed at 20 μm, the criterion for KOZ determination is considered to be a 10% change in carrier mobility gain [ 45 ]. As shown in Figure 8 , the hole carrier mobility gain change is apparently unfavorable for the 30 μm TSV diameter design with 700 MPa RS.…”

Section: Resultsmentioning

confidence: 99%

“…Accordingly, the virtual thermal strain approach has been proposed and validated, and it can be utilized to simulate lattice mismatch strain [ 44 ]. Its accuracy and feasibility have been validated through a comparison with literature data and analytically derived stress/strain formulas [ 45 , 46 ]. The lattice constant of concerned materials is calculated to estimate the subsequent lattice mismatch strain.…”

Section: Fundamental Theories Of 2d Analytical Stress Solution Lattice Stress Estimation Approach and Piezoresistance Behavior For Stressmentioning

confidence: 99%

See 1 more Smart Citation

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique

Huang

Lee

2021

Materials

Self Cite

View full text Add to dashboard Cite

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Fundamental Theories Of 2d Analytical Stress Solution Lattice Stress Estimation Approach and Piezoresistance Behavior For Stressmentioning

confidence: 99%